0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 =================
0004 PCI Test Function
0005 =================
0006
0007 :Author: Kishon Vijay Abraham I <kishon@ti.com>
0008
0009 Traditionally PCI RC has always been validated by using standard
0010 PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
0011 However with the addition of EP-core in linux kernel, it is possible
0012 to configure a PCI controller that can operate in EP mode to work as
0013 a test device.
0014
0015 The PCI endpoint test device is a virtual device (defined in software)
0016 used to test the endpoint functionality and serve as a sample driver
0017 for other PCI endpoint devices (to use the EP framework).
0018
0019 The PCI endpoint test device has the following registers:
0020
0021 1) PCI_ENDPOINT_TEST_MAGIC
0022 2) PCI_ENDPOINT_TEST_COMMAND
0023 3) PCI_ENDPOINT_TEST_STATUS
0024 4) PCI_ENDPOINT_TEST_SRC_ADDR
0025 5) PCI_ENDPOINT_TEST_DST_ADDR
0026 6) PCI_ENDPOINT_TEST_SIZE
0027 7) PCI_ENDPOINT_TEST_CHECKSUM
0028 8) PCI_ENDPOINT_TEST_IRQ_TYPE
0029 9) PCI_ENDPOINT_TEST_IRQ_NUMBER
0030
0031 * PCI_ENDPOINT_TEST_MAGIC
0032
0033 This register will be used to test BAR0. A known pattern will be written
0034 and read back from MAGIC register to verify BAR0.
0035
0036 * PCI_ENDPOINT_TEST_COMMAND
0037
0038 This register will be used by the host driver to indicate the function
0039 that the endpoint device must perform.
0040
0041 ======== ================================================================
0042 Bitfield Description
0043 ======== ================================================================
0044 Bit 0 raise legacy IRQ
0045 Bit 1 raise MSI IRQ
0046 Bit 2 raise MSI-X IRQ
0047 Bit 3 read command (read data from RC buffer)
0048 Bit 4 write command (write data to RC buffer)
0049 Bit 5 copy command (copy data from one RC buffer to another RC buffer)
0050 ======== ================================================================
0051
0052 * PCI_ENDPOINT_TEST_STATUS
0053
0054 This register reflects the status of the PCI endpoint device.
0055
0056 ======== ==============================
0057 Bitfield Description
0058 ======== ==============================
0059 Bit 0 read success
0060 Bit 1 read fail
0061 Bit 2 write success
0062 Bit 3 write fail
0063 Bit 4 copy success
0064 Bit 5 copy fail
0065 Bit 6 IRQ raised
0066 Bit 7 source address is invalid
0067 Bit 8 destination address is invalid
0068 ======== ==============================
0069
0070 * PCI_ENDPOINT_TEST_SRC_ADDR
0071
0072 This register contains the source address (RC buffer address) for the
0073 COPY/READ command.
0074
0075 * PCI_ENDPOINT_TEST_DST_ADDR
0076
0077 This register contains the destination address (RC buffer address) for
0078 the COPY/WRITE command.
0079
0080 * PCI_ENDPOINT_TEST_IRQ_TYPE
0081
0082 This register contains the interrupt type (Legacy/MSI) triggered
0083 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
0084
0085 Possible types:
0086
0087 ====== ==
0088 Legacy 0
0089 MSI 1
0090 MSI-X 2
0091 ====== ==
0092
0093 * PCI_ENDPOINT_TEST_IRQ_NUMBER
0094
0095 This register contains the triggered ID interrupt.
0096
0097 Admissible values:
0098
0099 ====== ===========
0100 Legacy 0
0101 MSI [1 .. 32]
0102 MSI-X [1 .. 2048]
0103 ====== ===========
