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OSCL-LXR

 
 

    


0001 What:           /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
0002 Date:           November 2014
0003 KernelVersion:  3.19
0004 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0005 Description:    (RW) Disables write access to the Trace RAM by stopping the
0006                 formatter after a defined number of words have been stored
0007                 following the trigger event. Additional interface for this
0008                 driver are expected to be added as it matures.
0009 
0010 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
0011 Date:           March 2016
0012 KernelVersion:  4.7
0013 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0014 Description:    (Read) Defines the size, in 32-bit words, of the local RAM buffer.
0015                 The value is read directly from HW register RSZ, 0x004.
0016 
0017 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
0018 Date:           March 2016
0019 KernelVersion:  4.7
0020 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0021 Description:    (Read) Shows the value held by the TMC status register.  The value
0022                 is read directly from HW register STS, 0x00C.
0023 
0024 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
0025 Date:           March 2016
0026 KernelVersion:  4.7
0027 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0028 Description:    (Read) Shows the value held by the TMC RAM Read Pointer register
0029                 that is used to read entries from the Trace RAM over the APB
0030                 interface.  The value is read directly from HW register RRP,
0031                 0x014.
0032 
0033 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
0034 Date:           March 2016
0035 KernelVersion:  4.7
0036 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0037 Description:    (Read) Shows the value held by the TMC RAM Write Pointer register
0038                 that is used to sets the write pointer to write entries from
0039                 the CoreSight bus into the Trace RAM. The value is read directly
0040                 from HW register RWP, 0x018.
0041 
0042 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
0043 Date:           March 2016
0044 KernelVersion:  4.7
0045 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0046 Description:    (Read) Similar to "trigger_cntr" above except that this value is
0047                 read directly from HW register TRG, 0x01C.
0048 
0049 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
0050 Date:           March 2016
0051 KernelVersion:  4.7
0052 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0053 Description:    (Read) Shows the value held by the TMC Control register. The value
0054                 is read directly from HW register CTL, 0x020.
0055 
0056 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
0057 Date:           March 2016
0058 KernelVersion:  4.7
0059 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0060 Description:    (Read) Shows the value held by the TMC Formatter and Flush Status
0061                 register.  The value is read directly from HW register FFSR,
0062                 0x300.
0063 
0064 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
0065 Date:           March 2016
0066 KernelVersion:  4.7
0067 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0068 Description:    (Read) Shows the value held by the TMC Formatter and Flush Control
0069                 register.  The value is read directly from HW register FFCR,
0070                 0x304.
0071 
0072 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
0073 Date:           March 2016
0074 KernelVersion:  4.7
0075 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0076 Description:    (Read) Shows the value held by the TMC Mode register, which
0077                 indicate the mode the device has been configured to enact.  The
0078                 The value is read directly from the MODE register, 0x028.
0079 
0080 What:           /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
0081 Date:           March 2016
0082 KernelVersion:  4.7
0083 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0084 Description:    (Read) Indicates the capabilities of the Coresight TMC.
0085                 The value is read directly from the DEVID register, 0xFC8,
0086 
0087 What:           /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size
0088 Date:           December 2018
0089 KernelVersion:  4.19
0090 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
0091 Description:    (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
0092                 mode. Writable only for TMC-ETR configurations. The value
0093                 should be aligned to the kernel pagesize.