0001 What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
0002 Date: April 2016
0003 KernelVersion: 4.7
0004 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0005 Description: (RW) Enable/disable tracing on this specific trace macrocell.
0006 Enabling the trace macrocell implies it has been configured
0007 properly and a sink has been identified for it. The path
0008 of coresight components linking the source to the sink is
0009 configured and managed automatically by the coresight framework.
0010
0011 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
0012 Date: April 2016
0013 KernelVersion: 4.7
0014 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0015 Description: (RW) Provides access to the HW event enable register, used in
0016 conjunction with HW event bank select register.
0017
0018 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
0019 Date: April 2016
0020 KernelVersion: 4.7
0021 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0022 Description: (RW) Gives access to the HW event block select register
0023 (STMHEBSR) in order to configure up to 256 channels. Used in
0024 conjunction with "hwevent_enable" register as described above.
0025
0026 What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
0027 Date: April 2016
0028 KernelVersion: 4.7
0029 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0030 Description: (RW) Provides access to the stimulus port enable register
0031 (STMSPER). Used in conjunction with "port_select" described
0032 below.
0033
0034 What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
0035 Date: April 2016
0036 KernelVersion: 4.7
0037 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0038 Description: (RW) Used to determine which bank of stimulus port bit in
0039 register STMSPER (see above) apply to.
0040
0041 What: /sys/bus/coresight/devices/<memory_map>.stm/status
0042 Date: April 2016
0043 KernelVersion: 4.7
0044 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0045 Description: (Read) List various control and status registers. The specific
0046 layout and content is driver specific.
0047
0048 What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
0049 Date: April 2016
0050 KernelVersion: 4.7
0051 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0052 Description: (RW) Holds the trace ID that will appear in the trace stream
0053 coming from this trace entity.
