0001 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
0002 Date: November 2014
0003 KernelVersion: 3.19
0004 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0005 Description: (RW) Enable/disable tracing on this specific trace entiry.
0006 Enabling a source implies the source has been configured
0007 properly and a sink has been identidifed for it. The path
0008 of coresight components linking the source to the sink is
0009 configured and managed automatically by the coresight framework.
0010
0011 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
0012 Date: November 2014
0013 KernelVersion: 3.19
0014 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0015 Description: Select which address comparator or pair (of comparators) to
0016 work with.
0017
0018 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
0019 Date: November 2014
0020 KernelVersion: 3.19
0021 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0022 Description: (RW) Used in conjunction with @addr_idx. Specifies
0023 characteristics about the address comparator being configure,
0024 for example the access type, the kind of instruction to trace,
0025 processor contect ID to trigger on, etc. Individual fields in
0026 the access type register may vary on the version of the trace
0027 entity.
0028
0029 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
0030 Date: November 2014
0031 KernelVersion: 3.19
0032 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0033 Description: (RW) Used in conjunction with @addr_idx. Specifies the range of
0034 addresses to trigger on. Inclusion or exclusion is specificed
0035 in the corresponding access type register.
0036
0037 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
0038 Date: November 2014
0039 KernelVersion: 3.19
0040 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0041 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
0042 address to trigger on, highly influenced by the configuration
0043 options of the corresponding access type register.
0044
0045 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
0046 Date: November 2014
0047 KernelVersion: 3.19
0048 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0049 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
0050 address to start tracing on, highly influenced by the
0051 configuration options of the corresponding access type register.
0052
0053 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
0054 Date: November 2014
0055 KernelVersion: 3.19
0056 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0057 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
0058 address to stop tracing on, highly influenced by the
0059 configuration options of the corresponding access type register.
0060
0061 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
0062 Date: November 2014
0063 KernelVersion: 3.19
0064 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0065 Description: (RW) Specifies the counter to work on.
0066
0067 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
0068 Date: November 2014
0069 KernelVersion: 3.19
0070 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0071 Description: (RW) Used in conjunction with cntr_idx, give access to the
0072 counter event register.
0073
0074 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
0075 Date: November 2014
0076 KernelVersion: 3.19
0077 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0078 Description: (RW) Used in conjunction with cntr_idx, give access to the
0079 counter value register.
0080
0081 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val
0082 Date: November 2014
0083 KernelVersion: 3.19
0084 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0085 Description: (RW) Used in conjunction with cntr_idx, give access to the
0086 counter reload value register.
0087
0088 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event
0089 Date: November 2014
0090 KernelVersion: 3.19
0091 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0092 Description: (RW) Used in conjunction with cntr_idx, give access to the
0093 counter reload event register.
0094
0095 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx
0096 Date: November 2014
0097 KernelVersion: 3.19
0098 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0099 Description: (RW) Specifies the index of the context ID register to be
0100 selected.
0101
0102 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask
0103 Date: November 2014
0104 KernelVersion: 3.19
0105 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0106 Description: (RW) Mask to apply to all the context ID comparator.
0107
0108 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid
0109 Date: November 2014
0110 KernelVersion: 3.19
0111 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0112 Description: (RW) Used with the ctxid_idx, specify with context ID to trigger
0113 on.
0114
0115 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event
0116 Date: November 2014
0117 KernelVersion: 3.19
0118 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0119 Description: (RW) Defines which event triggers a trace.
0120
0121 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr
0122 Date: November 2014
0123 KernelVersion: 3.19
0124 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0125 Description: (RW) Gives access to the ETM status register, which holds
0126 programming information and status on certains events.
0127
0128 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level
0129 Date: November 2014
0130 KernelVersion: 3.19
0131 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0132 Description: (RW) Number of byte left in the fifo before considering it full.
0133 Depending on the tracer's version, can also hold threshold for
0134 data suppression.
0135
0136 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode
0137 Date: November 2014
0138 KernelVersion: 3.19
0139 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0140 Description: (RW) Interface with the driver's 'mode' field, controlling
0141 various aspect of the trace entity such as time stamping,
0142 context ID size and cycle accurate tracing. Driver specific
0143 and bound to change depending on the driver.
0144
0145 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp
0146 Date: November 2014
0147 KernelVersion: 3.19
0148 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0149 Description: (Read) Provides the number of address comparators pairs accessible
0150 on a trace unit, as specified by bit 3:0 of register ETMCCR.
0151
0152 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr
0153 Date: November 2014
0154 KernelVersion: 3.19
0155 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0156 Description: (Read) Provides the number of counters accessible on a trace unit,
0157 as specified by bit 15:13 of register ETMCCR.
0158
0159 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp
0160 Date: November 2014
0161 KernelVersion: 3.19
0162 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0163 Description: (Read) Provides the number of context ID comparator available on a
0164 trace unit, as specified by bit 25:24 of register ETMCCR.
0165
0166 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset
0167 Date: November 2014
0168 KernelVersion: 3.19
0169 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0170 Description: (Write) Cancels all configuration on a trace unit and set it back
0171 to its boot configuration.
0172
0173 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event
0174 Date: November 2014
0175 KernelVersion: 3.19
0176 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0177 Description: (RW) Defines the event that causes the sequencer to transition
0178 from state 1 to state 2.
0179
0180 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event
0181 Date: November 2014
0182 KernelVersion: 3.19
0183 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0184 Description: (RW) Defines the event that causes the sequencer to transition
0185 from state 1 to state 3.
0186
0187 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event
0188 Date: November 2014
0189 KernelVersion: 3.19
0190 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0191 Description: (RW) Defines the event that causes the sequencer to transition
0192 from state 2 to state 1.
0193
0194 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event
0195 Date: November 2014
0196 KernelVersion: 3.19
0197 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0198 Description: (RW) Defines the event that causes the sequencer to transition
0199 from state 2 to state 3.
0200
0201 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event
0202 Date: November 2014
0203 KernelVersion: 3.19
0204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0205 Description: (RW) Defines the event that causes the sequencer to transition
0206 from state 3 to state 1.
0207
0208 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event
0209 Date: November 2014
0210 KernelVersion: 3.19
0211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0212 Description: (RW) Defines the event that causes the sequencer to transition
0213 from state 3 to state 2.
0214
0215 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state
0216 Date: November 2014
0217 KernelVersion: 3.19
0218 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0219 Description: (Read) Holds the current state of the sequencer.
0220
0221 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq
0222 Date: November 2014
0223 KernelVersion: 3.19
0224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0225 Description: (RW) Holds the trace synchronization frequency value - must be
0226 programmed with the various implementation behavior in mind.
0227
0228 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event
0229 Date: November 2014
0230 KernelVersion: 3.19
0231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0232 Description: (RW) Defines an event that requests the insertion of a timestamp
0233 into the trace stream.
0234
0235 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid
0236 Date: November 2014
0237 KernelVersion: 3.19
0238 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0239 Description: (RW) Holds the trace ID that will appear in the trace stream
0240 coming from this trace entity.
0241
0242 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event
0243 Date: November 2014
0244 KernelVersion: 3.19
0245 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0246 Description: (RW) Define the event that controls the trigger.
0247
0248 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu
0249 Date: October 2015
0250 KernelVersion: 4.4
0251 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0252 Description: (RO) Holds the cpu number this tracer is affined to.
0253
0254 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
0255 Date: September 2015
0256 KernelVersion: 4.4
0257 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0258 Description: (RO) Print the content of the ETM Configuration Code register
0259 (0x004). The value is read directly from the HW.
0260
0261 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer
0262 Date: September 2015
0263 KernelVersion: 4.4
0264 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0265 Description: (RO) Print the content of the ETM Configuration Code Extension
0266 register (0x1e8). The value is read directly from the HW.
0267
0268 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr
0269 Date: September 2015
0270 KernelVersion: 4.4
0271 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0272 Description: (RO) Print the content of the ETM System Configuration
0273 register (0x014). The value is read directly from the HW.
0274
0275 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr
0276 Date: September 2015
0277 KernelVersion: 4.4
0278 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0279 Description: (RO) Print the content of the ETM ID register (0x1e4). The
0280 value is read directly from the HW.
0281
0282 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr
0283 Date: September 2015
0284 KernelVersion: 4.4
0285 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0286 Description: (RO) Print the content of the ETM Main Control register (0x000).
0287 The value is read directly from the HW.
0288
0289 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr
0290 Date: September 2015
0291 KernelVersion: 4.4
0292 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0293 Description: (RO) Print the content of the ETM Trace ID register (0x200).
0294 The value is read directly from the HW.
0295
0296 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr
0297 Date: September 2015
0298 KernelVersion: 4.4
0299 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0300 Description: (RO) Print the content of the ETM Trace Enable Event register
0301 (0x020). The value is read directly from the HW.
0302
0303 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr
0304 Date: September 2015
0305 KernelVersion: 4.4
0306 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0307 Description: (RO) Print the content of the ETM Trace Start/Stop Conrol
0308 register (0x018). The value is read directly from the HW.
0309
0310 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1
0311 Date: September 2015
0312 KernelVersion: 4.4
0313 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0314 Description: (RO) Print the content of the ETM Enable Conrol #1
0315 register (0x024). The value is read directly from the HW.
0316
0317 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2
0318 Date: September 2015
0319 KernelVersion: 4.4
0320 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0321 Description: (RO) Print the content of the ETM Enable Conrol #2
0322 register (0x01c). The value is read directly from the HW.
