0001 What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink
0002 Date: November 2014
0003 KernelVersion: 3.19
0004 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0005 Description: (RW) Add/remove a sink from a trace path. There can be multiple
0006 source for a single sink.
0007
0008 ex::
0009
0010 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
0011
0012 What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
0013 Date: November 2014
0014 KernelVersion: 3.19
0015 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0016 Description: (RW) Disables write access to the Trace RAM by stopping the
0017 formatter after a defined number of words have been stored
0018 following the trigger event. The number of 32-bit words written
0019 into the Trace RAM following the trigger event is equal to the
0020 value stored in this register+1 (from ARM ETB-TRM).
0021
0022 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
0023 Date: March 2016
0024 KernelVersion: 4.7
0025 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0026 Description: (Read) Defines the depth, in words, of the trace RAM in powers of
0027 2. The value is read directly from HW register RDP, 0x004.
0028
0029 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
0030 Date: March 2016
0031 KernelVersion: 4.7
0032 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0033 Description: (Read) Shows the value held by the ETB status register. The value
0034 is read directly from HW register STS, 0x00C.
0035
0036 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
0037 Date: March 2016
0038 KernelVersion: 4.7
0039 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0040 Description: (Read) Shows the value held by the ETB RAM Read Pointer register
0041 that is used to read entries from the Trace RAM over the APB
0042 interface. The value is read directly from HW register RRP,
0043 0x014.
0044
0045 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
0046 Date: March 2016
0047 KernelVersion: 4.7
0048 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0049 Description: (Read) Shows the value held by the ETB RAM Write Pointer register
0050 that is used to sets the write pointer to write entries from
0051 the CoreSight bus into the Trace RAM. The value is read directly
0052 from HW register RWP, 0x018.
0053
0054 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
0055 Date: March 2016
0056 KernelVersion: 4.7
0057 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0058 Description: (Read) Similar to "trigger_cntr" above except that this value is
0059 read directly from HW register TRG, 0x01C.
0060
0061 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
0062 Date: March 2016
0063 KernelVersion: 4.7
0064 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0065 Description: (Read) Shows the value held by the ETB Control register. The value
0066 is read directly from HW register CTL, 0x020.
0067
0068 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
0069 Date: March 2016
0070 KernelVersion: 4.7
0071 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0072 Description: (Read) Shows the value held by the ETB Formatter and Flush Status
0073 register. The value is read directly from HW register FFSR,
0074 0x300.
0075
0076 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
0077 Date: March 2016
0078 KernelVersion: 4.7
0079 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
0080 Description: (Read) Shows the value held by the ETB Formatter and Flush Control
0081 register. The value is read directly from HW register FFCR,
0082 0x304.
