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0001 /*
0002  * DDR addressing details and AC timing parameters from JEDEC specs
0003  *
0004  * Copyright (C) 2012 Texas Instruments, Inc.
0005  *
0006  * Aneesh V <aneesh@ti.com>
0007  *
0008  * This program is free software; you can redistribute it and/or modify
0009  * it under the terms of the GNU General Public License version 2 as
0010  * published by the Free Software Foundation.
0011  */
0012 
0013 #include <memory/jedec_ddr.h>
0014 #include <linux/module.h>
0015 
0016 /* LPDDR2 addressing details from JESD209-2 section 2.4 */
0017 const struct lpddr2_addressing
0018     lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
0019     {B4, T_REFI_15_6, T_RFC_90}, /* 64M */
0020     {B4, T_REFI_15_6, T_RFC_90}, /* 128M */
0021     {B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
0022     {B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
0023     {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
0024     {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
0025     {B8, T_REFI_3_9, T_RFC_130}, /* 4G */
0026     {B8, T_REFI_3_9, T_RFC_210}, /* 8G */
0027     {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
0028     {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
0029 };
0030 EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
0031 
0032 /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
0033 const struct lpddr2_timings
0034     lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
0035     /* Speed bin 400(200 MHz) */
0036     [0] = {
0037         .max_freq   = 200000000,
0038         .min_freq   = 10000000,
0039         .tRPab      = 21000,
0040         .tRCD       = 18000,
0041         .tWR        = 15000,
0042         .tRAS_min   = 42000,
0043         .tRRD       = 10000,
0044         .tWTR       = 10000,
0045         .tXP        = 7500,
0046         .tRTP       = 7500,
0047         .tCKESR     = 15000,
0048         .tDQSCK_max = 5500,
0049         .tFAW       = 50000,
0050         .tZQCS      = 90000,
0051         .tZQCL      = 360000,
0052         .tZQinit    = 1000000,
0053         .tRAS_max_ns    = 70000,
0054         .tDQSCK_max_derated = 6000,
0055     },
0056     /* Speed bin 533(266 MHz) */
0057     [1] = {
0058         .max_freq   = 266666666,
0059         .min_freq   = 10000000,
0060         .tRPab      = 21000,
0061         .tRCD       = 18000,
0062         .tWR        = 15000,
0063         .tRAS_min   = 42000,
0064         .tRRD       = 10000,
0065         .tWTR       = 7500,
0066         .tXP        = 7500,
0067         .tRTP       = 7500,
0068         .tCKESR     = 15000,
0069         .tDQSCK_max = 5500,
0070         .tFAW       = 50000,
0071         .tZQCS      = 90000,
0072         .tZQCL      = 360000,
0073         .tZQinit    = 1000000,
0074         .tRAS_max_ns    = 70000,
0075         .tDQSCK_max_derated = 6000,
0076     },
0077     /* Speed bin 800(400 MHz) */
0078     [2] = {
0079         .max_freq   = 400000000,
0080         .min_freq   = 10000000,
0081         .tRPab      = 21000,
0082         .tRCD       = 18000,
0083         .tWR        = 15000,
0084         .tRAS_min   = 42000,
0085         .tRRD       = 10000,
0086         .tWTR       = 7500,
0087         .tXP        = 7500,
0088         .tRTP       = 7500,
0089         .tCKESR     = 15000,
0090         .tDQSCK_max = 5500,
0091         .tFAW       = 50000,
0092         .tZQCS      = 90000,
0093         .tZQCL      = 360000,
0094         .tZQinit    = 1000000,
0095         .tRAS_max_ns    = 70000,
0096         .tDQSCK_max_derated = 6000,
0097     },
0098     /* Speed bin 1066(533 MHz) */
0099     [3] = {
0100         .max_freq   = 533333333,
0101         .min_freq   = 10000000,
0102         .tRPab      = 21000,
0103         .tRCD       = 18000,
0104         .tWR        = 15000,
0105         .tRAS_min   = 42000,
0106         .tRRD       = 10000,
0107         .tWTR       = 7500,
0108         .tXP        = 7500,
0109         .tRTP       = 7500,
0110         .tCKESR     = 15000,
0111         .tDQSCK_max = 5500,
0112         .tFAW       = 50000,
0113         .tZQCS      = 90000,
0114         .tZQCL      = 360000,
0115         .tZQinit    = 1000000,
0116         .tRAS_max_ns    = 70000,
0117         .tDQSCK_max_derated = 5620,
0118     },
0119 };
0120 EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
0121 
0122 const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
0123     .tRPab      = 3,
0124     .tRCD       = 3,
0125     .tWR        = 3,
0126     .tRASmin    = 3,
0127     .tRRD       = 2,
0128     .tWTR       = 2,
0129     .tXP        = 2,
0130     .tRTP       = 2,
0131     .tCKE       = 3,
0132     .tCKESR     = 3,
0133     .tFAW       = 8
0134 };
0135 EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);