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0001 /*
0002  * Implement the default iomap interfaces
0003  *
0004  * (C) Copyright 2004 Linus Torvalds
0005  */
0006 #include <linux/pci.h>
0007 #include <linux/io.h>
0008 
0009 #include <linux/export.h>
0010 
0011 /*
0012  * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
0013  * access or a MMIO access, these functions don't care. The info is
0014  * encoded in the hardware mapping set up by the mapping functions
0015  * (or the cookie itself, depending on implementation and hw).
0016  *
0017  * The generic routines don't assume any hardware mappings, and just
0018  * encode the PIO/MMIO as part of the cookie. They coldly assume that
0019  * the MMIO IO mappings are not in the low address range.
0020  *
0021  * Architectures for which this is not true can't use this generic
0022  * implementation and should do their own copy.
0023  */
0024 
0025 #ifndef HAVE_ARCH_PIO_SIZE
0026 /*
0027  * We encode the physical PIO addresses (0-0xffff) into the
0028  * pointer by offsetting them with a constant (0x10000) and
0029  * assuming that all the low addresses are always PIO. That means
0030  * we can do some sanity checks on the low bits, and don't
0031  * need to just take things for granted.
0032  */
0033 #define PIO_OFFSET  0x10000UL
0034 #define PIO_MASK    0x0ffffUL
0035 #define PIO_RESERVED    0x40000UL
0036 #endif
0037 
0038 static void bad_io_access(unsigned long port, const char *access)
0039 {
0040     static int count = 10;
0041     if (count) {
0042         count--;
0043         WARN(1, KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
0044     }
0045 }
0046 
0047 /*
0048  * Ugly macros are a way of life.
0049  */
0050 #define IO_COND(addr, is_pio, is_mmio) do {         \
0051     unsigned long port = (unsigned long __force)addr;   \
0052     if (port >= PIO_RESERVED) {             \
0053         is_mmio;                    \
0054     } else if (port > PIO_OFFSET) {             \
0055         port &= PIO_MASK;               \
0056         is_pio;                     \
0057     } else                          \
0058         bad_io_access(port, #is_pio );          \
0059 } while (0)
0060 
0061 #ifndef pio_read16be
0062 #define pio_read16be(port) swab16(inw(port))
0063 #define pio_read32be(port) swab32(inl(port))
0064 #endif
0065 
0066 #ifndef mmio_read16be
0067 #define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
0068 #define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
0069 #endif
0070 
0071 unsigned int ioread8(void __iomem *addr)
0072 {
0073     IO_COND(addr, return inb(port), return readb(addr));
0074     return 0xff;
0075 }
0076 unsigned int ioread16(void __iomem *addr)
0077 {
0078     IO_COND(addr, return inw(port), return readw(addr));
0079     return 0xffff;
0080 }
0081 unsigned int ioread16be(void __iomem *addr)
0082 {
0083     IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
0084     return 0xffff;
0085 }
0086 unsigned int ioread32(void __iomem *addr)
0087 {
0088     IO_COND(addr, return inl(port), return readl(addr));
0089     return 0xffffffff;
0090 }
0091 unsigned int ioread32be(void __iomem *addr)
0092 {
0093     IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
0094     return 0xffffffff;
0095 }
0096 EXPORT_SYMBOL(ioread8);
0097 EXPORT_SYMBOL(ioread16);
0098 EXPORT_SYMBOL(ioread16be);
0099 EXPORT_SYMBOL(ioread32);
0100 EXPORT_SYMBOL(ioread32be);
0101 
0102 #ifndef pio_write16be
0103 #define pio_write16be(val,port) outw(swab16(val),port)
0104 #define pio_write32be(val,port) outl(swab32(val),port)
0105 #endif
0106 
0107 #ifndef mmio_write16be
0108 #define mmio_write16be(val,port) __raw_writew(be16_to_cpu(val),port)
0109 #define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
0110 #endif
0111 
0112 void iowrite8(u8 val, void __iomem *addr)
0113 {
0114     IO_COND(addr, outb(val,port), writeb(val, addr));
0115 }
0116 void iowrite16(u16 val, void __iomem *addr)
0117 {
0118     IO_COND(addr, outw(val,port), writew(val, addr));
0119 }
0120 void iowrite16be(u16 val, void __iomem *addr)
0121 {
0122     IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
0123 }
0124 void iowrite32(u32 val, void __iomem *addr)
0125 {
0126     IO_COND(addr, outl(val,port), writel(val, addr));
0127 }
0128 void iowrite32be(u32 val, void __iomem *addr)
0129 {
0130     IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
0131 }
0132 EXPORT_SYMBOL(iowrite8);
0133 EXPORT_SYMBOL(iowrite16);
0134 EXPORT_SYMBOL(iowrite16be);
0135 EXPORT_SYMBOL(iowrite32);
0136 EXPORT_SYMBOL(iowrite32be);
0137 
0138 /*
0139  * These are the "repeat MMIO read/write" functions.
0140  * Note the "__raw" accesses, since we don't want to
0141  * convert to CPU byte order. We write in "IO byte
0142  * order" (we also don't have IO barriers).
0143  */
0144 #ifndef mmio_insb
0145 static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
0146 {
0147     while (--count >= 0) {
0148         u8 data = __raw_readb(addr);
0149         *dst = data;
0150         dst++;
0151     }
0152 }
0153 static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
0154 {
0155     while (--count >= 0) {
0156         u16 data = __raw_readw(addr);
0157         *dst = data;
0158         dst++;
0159     }
0160 }
0161 static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
0162 {
0163     while (--count >= 0) {
0164         u32 data = __raw_readl(addr);
0165         *dst = data;
0166         dst++;
0167     }
0168 }
0169 #endif
0170 
0171 #ifndef mmio_outsb
0172 static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
0173 {
0174     while (--count >= 0) {
0175         __raw_writeb(*src, addr);
0176         src++;
0177     }
0178 }
0179 static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
0180 {
0181     while (--count >= 0) {
0182         __raw_writew(*src, addr);
0183         src++;
0184     }
0185 }
0186 static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
0187 {
0188     while (--count >= 0) {
0189         __raw_writel(*src, addr);
0190         src++;
0191     }
0192 }
0193 #endif
0194 
0195 void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
0196 {
0197     IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
0198 }
0199 void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
0200 {
0201     IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
0202 }
0203 void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
0204 {
0205     IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
0206 }
0207 EXPORT_SYMBOL(ioread8_rep);
0208 EXPORT_SYMBOL(ioread16_rep);
0209 EXPORT_SYMBOL(ioread32_rep);
0210 
0211 void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
0212 {
0213     IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
0214 }
0215 void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
0216 {
0217     IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
0218 }
0219 void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
0220 {
0221     IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
0222 }
0223 EXPORT_SYMBOL(iowrite8_rep);
0224 EXPORT_SYMBOL(iowrite16_rep);
0225 EXPORT_SYMBOL(iowrite32_rep);
0226 
0227 #ifdef CONFIG_HAS_IOPORT_MAP
0228 /* Create a virtual mapping cookie for an IO port range */
0229 void __iomem *ioport_map(unsigned long port, unsigned int nr)
0230 {
0231     if (port > PIO_MASK)
0232         return NULL;
0233     return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
0234 }
0235 
0236 void ioport_unmap(void __iomem *addr)
0237 {
0238     /* Nothing to do */
0239 }
0240 EXPORT_SYMBOL(ioport_map);
0241 EXPORT_SYMBOL(ioport_unmap);
0242 #endif /* CONFIG_HAS_IOPORT_MAP */
0243 
0244 #ifdef CONFIG_PCI
0245 /* Hide the details if this is a MMIO or PIO address space and just do what
0246  * you expect in the correct way. */
0247 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
0248 {
0249     IO_COND(addr, /* nothing */, iounmap(addr));
0250 }
0251 EXPORT_SYMBOL(pci_iounmap);
0252 #endif /* CONFIG_PCI */