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0001 /*
0002  *  linux/drivers/net/ethernet/ibm/ehea/ehea.h
0003  *
0004  *  eHEA ethernet device driver for IBM eServer System p
0005  *
0006  *  (C) Copyright IBM Corp. 2006
0007  *
0008  *  Authors:
0009  *       Christoph Raisch <raisch@de.ibm.com>
0010  *       Jan-Bernd Themann <themann@de.ibm.com>
0011  *       Thomas Klein <tklein@de.ibm.com>
0012  *
0013  *
0014  * This program is free software; you can redistribute it and/or modify
0015  * it under the terms of the GNU General Public License as published by
0016  * the Free Software Foundation; either version 2, or (at your option)
0017  * any later version.
0018  *
0019  * This program is distributed in the hope that it will be useful,
0020  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0021  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0022  * GNU General Public License for more details.
0023  *
0024  * You should have received a copy of the GNU General Public License
0025  * along with this program; if not, write to the Free Software
0026  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
0027  */
0028 
0029 #ifndef __EHEA_H__
0030 #define __EHEA_H__
0031 
0032 #include <linux/module.h>
0033 #include <linux/ethtool.h>
0034 #include <linux/vmalloc.h>
0035 #include <linux/if_vlan.h>
0036 
0037 #include <asm/ibmebus.h>
0038 #include <asm/io.h>
0039 
0040 #define DRV_NAME    "ehea"
0041 #define DRV_VERSION "EHEA_0107"
0042 
0043 /* eHEA capability flags */
0044 #define DLPAR_PORT_ADD_REM 1
0045 #define DLPAR_MEM_ADD      2
0046 #define DLPAR_MEM_REM      4
0047 #define EHEA_CAPABILITIES  (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
0048 
0049 #define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
0050     | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
0051 
0052 #define EHEA_MAX_ENTRIES_RQ1 32767
0053 #define EHEA_MAX_ENTRIES_RQ2 16383
0054 #define EHEA_MAX_ENTRIES_RQ3 16383
0055 #define EHEA_MAX_ENTRIES_SQ  32767
0056 #define EHEA_MIN_ENTRIES_QP  127
0057 
0058 #define EHEA_SMALL_QUEUES
0059 
0060 #ifdef EHEA_SMALL_QUEUES
0061 #define EHEA_MAX_CQE_COUNT      1023
0062 #define EHEA_DEF_ENTRIES_SQ     1023
0063 #define EHEA_DEF_ENTRIES_RQ1    1023
0064 #define EHEA_DEF_ENTRIES_RQ2    1023
0065 #define EHEA_DEF_ENTRIES_RQ3    511
0066 #else
0067 #define EHEA_MAX_CQE_COUNT      4080
0068 #define EHEA_DEF_ENTRIES_SQ     4080
0069 #define EHEA_DEF_ENTRIES_RQ1    8160
0070 #define EHEA_DEF_ENTRIES_RQ2    2040
0071 #define EHEA_DEF_ENTRIES_RQ3    2040
0072 #endif
0073 
0074 #define EHEA_MAX_ENTRIES_EQ 20
0075 
0076 #define EHEA_SG_SQ  2
0077 #define EHEA_SG_RQ1 1
0078 #define EHEA_SG_RQ2 0
0079 #define EHEA_SG_RQ3 0
0080 
0081 #define EHEA_MAX_PACKET_SIZE    9022    /* for jumbo frames */
0082 #define EHEA_RQ2_PKT_SIZE       2048
0083 #define EHEA_L_PKT_SIZE         256 /* low latency */
0084 
0085 /* Send completion signaling */
0086 
0087 /* Protection Domain Identifier */
0088 #define EHEA_PD_ID        0xaabcdeff
0089 
0090 #define EHEA_RQ2_THRESHOLD     1
0091 #define EHEA_RQ3_THRESHOLD     4    /* use RQ3 threshold of 2048 bytes */
0092 
0093 #define EHEA_SPEED_10G         10000
0094 #define EHEA_SPEED_1G           1000
0095 #define EHEA_SPEED_100M          100
0096 #define EHEA_SPEED_10M            10
0097 #define EHEA_SPEED_AUTONEG         0
0098 
0099 /* Broadcast/Multicast registration types */
0100 #define EHEA_BCMC_SCOPE_ALL 0x08
0101 #define EHEA_BCMC_SCOPE_SINGLE  0x00
0102 #define EHEA_BCMC_MULTICAST 0x04
0103 #define EHEA_BCMC_BROADCAST 0x00
0104 #define EHEA_BCMC_UNTAGGED  0x02
0105 #define EHEA_BCMC_TAGGED    0x00
0106 #define EHEA_BCMC_VLANID_ALL    0x01
0107 #define EHEA_BCMC_VLANID_SINGLE 0x00
0108 
0109 #define EHEA_CACHE_LINE          128
0110 
0111 /* Memory Regions */
0112 #define EHEA_MR_ACC_CTRL       0x00800000
0113 
0114 #define EHEA_BUSMAP_START      0x8000000000000000ULL
0115 #define EHEA_INVAL_ADDR        0xFFFFFFFFFFFFFFFFULL
0116 #define EHEA_DIR_INDEX_SHIFT 13                   /* 8k Entries in 64k block */
0117 #define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
0118 #define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
0119 #define EHEA_MAP_SIZE (0x10000)                   /* currently fixed map size */
0120 #define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
0121 
0122 
0123 #define EHEA_WATCH_DOG_TIMEOUT 10*HZ
0124 
0125 /* utility functions */
0126 
0127 void ehea_dump(void *adr, int len, char *msg);
0128 
0129 #define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
0130 
0131 #define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
0132 
0133 #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
0134 
0135 #define EHEA_BMASK_MASK(mask) \
0136     (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
0137 
0138 #define EHEA_BMASK_SET(mask, value) \
0139     ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
0140 
0141 #define EHEA_BMASK_GET(mask, value) \
0142     (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
0143 
0144 /*
0145  * Generic ehea page
0146  */
0147 struct ehea_page {
0148     u8 entries[PAGE_SIZE];
0149 };
0150 
0151 /*
0152  * Generic queue in linux kernel virtual memory
0153  */
0154 struct hw_queue {
0155     u64 current_q_offset;       /* current queue entry */
0156     struct ehea_page **queue_pages; /* array of pages belonging to queue */
0157     u32 qe_size;            /* queue entry size */
0158     u32 queue_length;           /* queue length allocated in bytes */
0159     u32 pagesize;
0160     u32 toggle_state;       /* toggle flag - per page */
0161     u32 reserved;           /* 64 bit alignment */
0162 };
0163 
0164 /*
0165  * For pSeries this is a 64bit memory address where
0166  * I/O memory is mapped into CPU address space
0167  */
0168 struct h_epa {
0169     void __iomem *addr;
0170 };
0171 
0172 struct h_epa_user {
0173     u64 addr;
0174 };
0175 
0176 struct h_epas {
0177     struct h_epa kernel;    /* kernel space accessible resource,
0178                    set to 0 if unused */
0179     struct h_epa_user user; /* user space accessible resource
0180                    set to 0 if unused */
0181 };
0182 
0183 /*
0184  * Memory map data structures
0185  */
0186 struct ehea_dir_bmap
0187 {
0188     u64 ent[EHEA_MAP_ENTRIES];
0189 };
0190 struct ehea_top_bmap
0191 {
0192     struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
0193 };
0194 struct ehea_bmap
0195 {
0196     struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
0197 };
0198 
0199 struct ehea_qp;
0200 struct ehea_cq;
0201 struct ehea_eq;
0202 struct ehea_port;
0203 struct ehea_av;
0204 
0205 /*
0206  * Queue attributes passed to ehea_create_qp()
0207  */
0208 struct ehea_qp_init_attr {
0209     /* input parameter */
0210     u32 qp_token;           /* queue token */
0211     u8 low_lat_rq1;
0212     u8 signalingtype;       /* cqe generation flag */
0213     u8 rq_count;            /* num of receive queues */
0214     u8 eqe_gen;             /* eqe generation flag */
0215     u16 max_nr_send_wqes;   /* max number of send wqes */
0216     u16 max_nr_rwqes_rq1;   /* max number of receive wqes */
0217     u16 max_nr_rwqes_rq2;
0218     u16 max_nr_rwqes_rq3;
0219     u8 wqe_size_enc_sq;
0220     u8 wqe_size_enc_rq1;
0221     u8 wqe_size_enc_rq2;
0222     u8 wqe_size_enc_rq3;
0223     u8 swqe_imm_data_len;   /* immediate data length for swqes */
0224     u16 port_nr;
0225     u16 rq2_threshold;
0226     u16 rq3_threshold;
0227     u64 send_cq_handle;
0228     u64 recv_cq_handle;
0229     u64 aff_eq_handle;
0230 
0231     /* output parameter */
0232     u32 qp_nr;
0233     u16 act_nr_send_wqes;
0234     u16 act_nr_rwqes_rq1;
0235     u16 act_nr_rwqes_rq2;
0236     u16 act_nr_rwqes_rq3;
0237     u8 act_wqe_size_enc_sq;
0238     u8 act_wqe_size_enc_rq1;
0239     u8 act_wqe_size_enc_rq2;
0240     u8 act_wqe_size_enc_rq3;
0241     u32 nr_sq_pages;
0242     u32 nr_rq1_pages;
0243     u32 nr_rq2_pages;
0244     u32 nr_rq3_pages;
0245     u32 liobn_sq;
0246     u32 liobn_rq1;
0247     u32 liobn_rq2;
0248     u32 liobn_rq3;
0249 };
0250 
0251 /*
0252  * Event Queue attributes, passed as parameter
0253  */
0254 struct ehea_eq_attr {
0255     u32 type;
0256     u32 max_nr_of_eqes;
0257     u8 eqe_gen;        /* generate eqe flag */
0258     u64 eq_handle;
0259     u32 act_nr_of_eqes;
0260     u32 nr_pages;
0261     u32 ist1;          /* Interrupt service token */
0262     u32 ist2;
0263     u32 ist3;
0264     u32 ist4;
0265 };
0266 
0267 
0268 /*
0269  * Event Queue
0270  */
0271 struct ehea_eq {
0272     struct ehea_adapter *adapter;
0273     struct hw_queue hw_queue;
0274     u64 fw_handle;
0275     struct h_epas epas;
0276     spinlock_t spinlock;
0277     struct ehea_eq_attr attr;
0278 };
0279 
0280 /*
0281  * HEA Queues
0282  */
0283 struct ehea_qp {
0284     struct ehea_adapter *adapter;
0285     u64 fw_handle;          /* QP handle for firmware calls */
0286     struct hw_queue hw_squeue;
0287     struct hw_queue hw_rqueue1;
0288     struct hw_queue hw_rqueue2;
0289     struct hw_queue hw_rqueue3;
0290     struct h_epas epas;
0291     struct ehea_qp_init_attr init_attr;
0292 };
0293 
0294 /*
0295  * Completion Queue attributes
0296  */
0297 struct ehea_cq_attr {
0298     /* input parameter */
0299     u32 max_nr_of_cqes;
0300     u32 cq_token;
0301     u64 eq_handle;
0302 
0303     /* output parameter */
0304     u32 act_nr_of_cqes;
0305     u32 nr_pages;
0306 };
0307 
0308 /*
0309  * Completion Queue
0310  */
0311 struct ehea_cq {
0312     struct ehea_adapter *adapter;
0313     u64 fw_handle;
0314     struct hw_queue hw_queue;
0315     struct h_epas epas;
0316     struct ehea_cq_attr attr;
0317 };
0318 
0319 /*
0320  * Memory Region
0321  */
0322 struct ehea_mr {
0323     struct ehea_adapter *adapter;
0324     u64 handle;
0325     u64 vaddr;
0326     u32 lkey;
0327 };
0328 
0329 /*
0330  * Port state information
0331  */
0332 struct port_stats {
0333     int poll_receive_errors;
0334     int queue_stopped;
0335     int err_tcp_cksum;
0336     int err_ip_cksum;
0337     int err_frame_crc;
0338 };
0339 
0340 #define EHEA_IRQ_NAME_SIZE 20
0341 
0342 /*
0343  * Queue SKB Array
0344  */
0345 struct ehea_q_skb_arr {
0346     struct sk_buff **arr;       /* skb array for queue */
0347     int len;                    /* array length */
0348     int index;          /* array index */
0349     int os_skbs;            /* rq2/rq3 only: outstanding skbs */
0350 };
0351 
0352 /*
0353  * Port resources
0354  */
0355 struct ehea_port_res {
0356     struct napi_struct napi;
0357     struct port_stats p_stats;
0358     struct ehea_mr send_mr;         /* send memory region */
0359     struct ehea_mr recv_mr;         /* receive memory region */
0360     struct ehea_port *port;
0361     char int_recv_name[EHEA_IRQ_NAME_SIZE];
0362     char int_send_name[EHEA_IRQ_NAME_SIZE];
0363     struct ehea_qp *qp;
0364     struct ehea_cq *send_cq;
0365     struct ehea_cq *recv_cq;
0366     struct ehea_eq *eq;
0367     struct ehea_q_skb_arr rq1_skba;
0368     struct ehea_q_skb_arr rq2_skba;
0369     struct ehea_q_skb_arr rq3_skba;
0370     struct ehea_q_skb_arr sq_skba;
0371     int sq_skba_size;
0372     int swqe_refill_th;
0373     atomic_t swqe_avail;
0374     int swqe_ll_count;
0375     u32 swqe_id_counter;
0376     u64 tx_packets;
0377     u64 tx_bytes;
0378     u64 rx_packets;
0379     u64 rx_bytes;
0380     int sq_restart_flag;
0381 };
0382 
0383 
0384 #define EHEA_MAX_PORTS 16
0385 
0386 #define EHEA_NUM_PORTRES_FW_HANDLES    6  /* QP handle, SendCQ handle,
0387                          RecvCQ handle, EQ handle,
0388                          SendMR handle, RecvMR handle */
0389 #define EHEA_NUM_PORT_FW_HANDLES       1  /* EQ handle */
0390 #define EHEA_NUM_ADAPTER_FW_HANDLES    2  /* MR handle, NEQ handle */
0391 
0392 struct ehea_adapter {
0393     u64 handle;
0394     struct platform_device *ofdev;
0395     struct ehea_port *port[EHEA_MAX_PORTS];
0396     struct ehea_eq *neq;       /* notification event queue */
0397     struct tasklet_struct neq_tasklet;
0398     struct ehea_mr mr;
0399     u32 pd;                    /* protection domain */
0400     u64 max_mc_mac;            /* max number of multicast mac addresses */
0401     int active_ports;
0402     struct list_head list;
0403 };
0404 
0405 
0406 struct ehea_mc_list {
0407     struct list_head list;
0408     u64 macaddr;
0409 };
0410 
0411 /* kdump support */
0412 struct ehea_fw_handle_entry {
0413     u64 adh;               /* Adapter Handle */
0414     u64 fwh;               /* Firmware Handle */
0415 };
0416 
0417 struct ehea_fw_handle_array {
0418     struct ehea_fw_handle_entry *arr;
0419     int num_entries;
0420     struct mutex lock;
0421 };
0422 
0423 struct ehea_bcmc_reg_entry {
0424     u64 adh;               /* Adapter Handle */
0425     u32 port_id;           /* Logical Port Id */
0426     u8 reg_type;           /* Registration Type */
0427     u64 macaddr;
0428 };
0429 
0430 struct ehea_bcmc_reg_array {
0431     struct ehea_bcmc_reg_entry *arr;
0432     int num_entries;
0433     spinlock_t lock;
0434 };
0435 
0436 #define EHEA_PORT_UP 1
0437 #define EHEA_PORT_DOWN 0
0438 #define EHEA_PHY_LINK_UP 1
0439 #define EHEA_PHY_LINK_DOWN 0
0440 #define EHEA_MAX_PORT_RES 16
0441 struct ehea_port {
0442     struct ehea_adapter *adapter;    /* adapter that owns this port */
0443     struct net_device *netdev;
0444     struct rtnl_link_stats64 stats;
0445     struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
0446     struct platform_device  ofdev; /* Open Firmware Device */
0447     struct ehea_mc_list *mc_list;    /* Multicast MAC addresses */
0448     struct ehea_eq *qp_eq;
0449     struct work_struct reset_task;
0450     struct delayed_work stats_work;
0451     struct mutex port_lock;
0452     char int_aff_name[EHEA_IRQ_NAME_SIZE];
0453     int allmulti;            /* Indicates IFF_ALLMULTI state */
0454     int promisc;             /* Indicates IFF_PROMISC state */
0455     int num_mcs;
0456     int resets;
0457     unsigned long flags;
0458     u64 mac_addr;
0459     u32 logical_port_id;
0460     u32 port_speed;
0461     u32 msg_enable;
0462     u32 sig_comp_iv;
0463     u32 state;
0464     u8 phy_link;
0465     u8 full_duplex;
0466     u8 autoneg;
0467     u8 num_def_qps;
0468     wait_queue_head_t swqe_avail_wq;
0469     wait_queue_head_t restart_wq;
0470 };
0471 
0472 struct port_res_cfg {
0473     int max_entries_rcq;
0474     int max_entries_scq;
0475     int max_entries_sq;
0476     int max_entries_rq1;
0477     int max_entries_rq2;
0478     int max_entries_rq3;
0479 };
0480 
0481 enum ehea_flag_bits {
0482     __EHEA_STOP_XFER,
0483     __EHEA_DISABLE_PORT_RESET
0484 };
0485 
0486 void ehea_set_ethtool_ops(struct net_device *netdev);
0487 int ehea_sense_port_attr(struct ehea_port *port);
0488 int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
0489 
0490 #endif  /* __EHEA_H__ */