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0001 /*
0002  * Copyright 2014 IBM Corp.
0003  *
0004  * This program is free software; you can redistribute it and/or
0005  * modify it under the terms of the GNU General Public License
0006  * as published by the Free Software Foundation; either version
0007  * 2 of the License, or (at your option) any later version.
0008  */
0009 
0010 #ifndef _CXL_H_
0011 #define _CXL_H_
0012 
0013 #include <linux/interrupt.h>
0014 #include <linux/semaphore.h>
0015 #include <linux/device.h>
0016 #include <linux/types.h>
0017 #include <linux/cdev.h>
0018 #include <linux/pid.h>
0019 #include <linux/io.h>
0020 #include <linux/pci.h>
0021 #include <linux/fs.h>
0022 #include <asm/cputable.h>
0023 #include <asm/mmu.h>
0024 #include <asm/reg.h>
0025 #include <misc/cxl-base.h>
0026 
0027 #include <misc/cxl.h>
0028 #include <uapi/misc/cxl.h>
0029 
0030 extern uint cxl_verbose;
0031 
0032 #define CXL_TIMEOUT 5
0033 
0034 /*
0035  * Bump version each time a user API change is made, whether it is
0036  * backwards compatible ot not.
0037  */
0038 #define CXL_API_VERSION 3
0039 #define CXL_API_VERSION_COMPATIBLE 1
0040 
0041 /*
0042  * Opaque types to avoid accidentally passing registers for the wrong MMIO
0043  *
0044  * At the end of the day, I'm not married to using typedef here, but it might
0045  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
0046  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
0047  *
0048  * I'm quite happy if these are changed back to #defines before upstreaming, it
0049  * should be little more than a regexp search+replace operation in this file.
0050  */
0051 typedef struct {
0052     const int x;
0053 } cxl_p1_reg_t;
0054 typedef struct {
0055     const int x;
0056 } cxl_p1n_reg_t;
0057 typedef struct {
0058     const int x;
0059 } cxl_p2n_reg_t;
0060 #define cxl_reg_off(reg) \
0061     (reg.x)
0062 
0063 /* Memory maps. Ref CXL Appendix A */
0064 
0065 /* PSL Privilege 1 Memory Map */
0066 /* Configuration and Control area */
0067 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
0068 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
0069 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
0070 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
0071 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
0072 /* Downloading */
0073 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
0074 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
0075 
0076 /* PSL Lookaside Buffer Management Area */
0077 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
0078 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
0079 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
0080 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
0081 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
0082 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
0083 
0084 /* 0x00C0:7EFF Implementation dependent area */
0085 /* PSL registers */
0086 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
0087 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
0088 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
0089 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
0090 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
0091 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
0092 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
0093 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
0094 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
0095 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
0096 /* XSL registers (Mellanox CX4) */
0097 static const cxl_p1_reg_t CXL_XSL_Timebase  = {0x0100};
0098 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
0099 static const cxl_p1_reg_t CXL_XSL_FEC       = {0x0158};
0100 static const cxl_p1_reg_t CXL_XSL_DSNCTL    = {0x0168};
0101 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
0102 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
0103 
0104 /* PSL Slice Privilege 1 Memory Map */
0105 /* Configuration Area */
0106 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
0107 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
0108 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
0109 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
0110 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
0111 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
0112 /* Memory Management and Lookaside Buffer Management */
0113 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
0114 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
0115 /* Pointer Area */
0116 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
0117 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
0118 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
0119 /* Control Area */
0120 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
0121 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
0122 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
0123 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
0124 /* 0xC0:FF Implementation Dependent Area */
0125 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
0126 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
0127 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
0128 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
0129 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
0130 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
0131 
0132 /* PSL Slice Privilege 2 Memory Map */
0133 /* Configuration and Control Area */
0134 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
0135 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
0136 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
0137 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
0138 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
0139 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
0140 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
0141 /* Segment Lookaside Buffer Management */
0142 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
0143 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
0144 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
0145 /* Interrupt Registers */
0146 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
0147 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
0148 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
0149 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
0150 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
0151 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
0152 /* AFU Registers */
0153 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
0154 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
0155 /* Work Element Descriptor */
0156 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
0157 /* 0x0C0:FFF Implementation Dependent Area */
0158 
0159 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
0160 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
0161 #define CXL_PSL_SPAP_Size_Shift 4
0162 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
0163 
0164 /****** CXL_PSL_Control ****************************************************/
0165 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
0166 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
0167 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
0168 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
0169 
0170 /****** CXL_PSL_DLCNTL *****************************************************/
0171 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
0172 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
0173 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
0174 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
0175 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
0176 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
0177 
0178 /****** CXL_PSL_SR_An ******************************************************/
0179 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
0180 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
0181 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
0182 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
0183 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
0184 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
0185 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
0186 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
0187 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
0188 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
0189 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
0190 
0191 /****** CXL_PSL_ID_An ****************************************************/
0192 #define CXL_PSL_ID_An_F (1ull << (63-31))
0193 #define CXL_PSL_ID_An_L (1ull << (63-30))
0194 
0195 /****** CXL_PSL_SERR_An ****************************************************/
0196 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
0197 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
0198 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
0199 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
0200 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
0201 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
0202 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
0203 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
0204 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
0205 #define CXL_PSL_SERR_An_AE  (1ull << (63-30))
0206 
0207 /****** CXL_PSL_SCNTL_An ****************************************************/
0208 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
0209 /* Programming Modes: */
0210 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
0211 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
0212 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
0213 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
0214 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
0215 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
0216 /* Purge Status (ro) */
0217 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
0218 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
0219 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
0220 /* Purge */
0221 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
0222 /* Suspend Status (ro) */
0223 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
0224 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
0225 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
0226 /* Suspend Control */
0227 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
0228 
0229 /* AFU Slice Enable Status (ro) */
0230 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
0231 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
0232 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
0233 /* AFU Slice Enable */
0234 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
0235 /* AFU Slice Reset status (ro) */
0236 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
0237 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
0238 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
0239 /* AFU Slice Reset */
0240 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
0241 
0242 /****** CXL_SSTP0/1_An ******************************************************/
0243 /* These top bits are for the segment that CONTAINS the segment table */
0244 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
0245 #define CXL_SSTP0_An_KS             (1ull << (63-2))
0246 #define CXL_SSTP0_An_KP             (1ull << (63-3))
0247 #define CXL_SSTP0_An_N              (1ull << (63-4))
0248 #define CXL_SSTP0_An_L              (1ull << (63-5))
0249 #define CXL_SSTP0_An_C              (1ull << (63-6))
0250 #define CXL_SSTP0_An_TA             (1ull << (63-7))
0251 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
0252 /* And finally, the virtual address & size of the segment table: */
0253 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
0254 #define CXL_SSTP0_An_SegTableSize_MASK \
0255     (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
0256 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
0257 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
0258 #define CXL_SSTP1_An_V              (1ull << (63-63))
0259 
0260 /****** CXL_PSL_SLBIE_[An] **************************************************/
0261 /* write: */
0262 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
0263 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
0264 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
0265 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
0266 /* read: */
0267 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
0268 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
0269 
0270 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
0271 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
0272 
0273 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
0274 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
0275 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
0276 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
0277 
0278 /****** CXL_PSL_AFUSEL ******************************************************/
0279 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
0280 
0281 /****** CXL_PSL_DSISR_An ****************************************************/
0282 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
0283 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
0284 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
0285 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
0286 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
0287 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
0288 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
0289 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
0290 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
0291 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
0292 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
0293 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
0294 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
0295 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
0296 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
0297 
0298 /****** CXL_PSL_TFC_An ******************************************************/
0299 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
0300 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
0301 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
0302 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
0303 
0304 /* cxl_process_element->software_status */
0305 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
0306 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
0307 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
0308 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
0309 
0310 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
0311  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
0312  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
0313  * of the hang pulse frequency.
0314  */
0315 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
0316 
0317 /* SPA->sw_command_status */
0318 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
0319 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
0320 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
0321 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
0322 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
0323 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
0324 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
0325 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
0326 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
0327 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
0328 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
0329 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
0330 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
0331 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
0332 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
0333 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
0334 
0335 #define CXL_MAX_SLICES 4
0336 #define MAX_AFU_MMIO_REGS 3
0337 
0338 #define CXL_MODE_TIME_SLICED 0x4
0339 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
0340 
0341 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
0342 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
0343 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
0344 
0345 enum cxl_context_status {
0346     CLOSED,
0347     OPENED,
0348     STARTED
0349 };
0350 
0351 enum prefault_modes {
0352     CXL_PREFAULT_NONE,
0353     CXL_PREFAULT_WED,
0354     CXL_PREFAULT_ALL,
0355 };
0356 
0357 enum cxl_attrs {
0358     CXL_ADAPTER_ATTRS,
0359     CXL_AFU_MASTER_ATTRS,
0360     CXL_AFU_ATTRS,
0361 };
0362 
0363 struct cxl_sste {
0364     __be64 esid_data;
0365     __be64 vsid_data;
0366 };
0367 
0368 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
0369 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
0370 
0371 struct cxl_afu_native {
0372     void __iomem *p1n_mmio;
0373     void __iomem *afu_desc_mmio;
0374     irq_hw_number_t psl_hwirq;
0375     unsigned int psl_virq;
0376     struct mutex spa_mutex;
0377     /*
0378      * Only the first part of the SPA is used for the process element
0379      * linked list. The only other part that software needs to worry about
0380      * is sw_command_status, which we store a separate pointer to.
0381      * Everything else in the SPA is only used by hardware
0382      */
0383     struct cxl_process_element *spa;
0384     __be64 *sw_command_status;
0385     unsigned int spa_size;
0386     int spa_order;
0387     int spa_max_procs;
0388     u64 pp_offset;
0389 };
0390 
0391 struct cxl_afu_guest {
0392     struct cxl_afu *parent;
0393     u64 handle;
0394     phys_addr_t p2n_phys;
0395     u64 p2n_size;
0396     int max_ints;
0397     bool handle_err;
0398     struct delayed_work work_err;
0399     int previous_state;
0400 };
0401 
0402 struct cxl_afu {
0403     struct cxl_afu_native *native;
0404     struct cxl_afu_guest *guest;
0405     irq_hw_number_t serr_hwirq;
0406     unsigned int serr_virq;
0407     char *psl_irq_name;
0408     char *err_irq_name;
0409     void __iomem *p2n_mmio;
0410     phys_addr_t psn_phys;
0411     u64 pp_size;
0412 
0413     struct cxl *adapter;
0414     struct device dev;
0415     struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
0416     struct device *chardev_s, *chardev_m, *chardev_d;
0417     struct idr contexts_idr;
0418     struct dentry *debugfs;
0419     struct mutex contexts_lock;
0420     spinlock_t afu_cntl_lock;
0421 
0422     /* AFU error buffer fields and bin attribute for sysfs */
0423     u64 eb_len, eb_offset;
0424     struct bin_attribute attr_eb;
0425 
0426     /* pointer to the vphb */
0427     struct pci_controller *phb;
0428 
0429     int pp_irqs;
0430     int irqs_max;
0431     int num_procs;
0432     int max_procs_virtualised;
0433     int slice;
0434     int modes_supported;
0435     int current_mode;
0436     int crs_num;
0437     u64 crs_len;
0438     u64 crs_offset;
0439     struct list_head crs;
0440     enum prefault_modes prefault_mode;
0441     bool psa;
0442     bool pp_psa;
0443     bool enabled;
0444 };
0445 
0446 
0447 struct cxl_irq_name {
0448     struct list_head list;
0449     char *name;
0450 };
0451 
0452 struct irq_avail {
0453     irq_hw_number_t offset;
0454     irq_hw_number_t range;
0455     unsigned long   *bitmap;
0456 };
0457 
0458 /*
0459  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
0460  * of these per AFU.  If in AFU directed there can be lots of these.
0461  */
0462 struct cxl_context {
0463     struct cxl_afu *afu;
0464 
0465     /* Problem state MMIO */
0466     phys_addr_t psn_phys;
0467     u64 psn_size;
0468 
0469     /* Used to unmap any mmaps when force detaching */
0470     struct address_space *mapping;
0471     struct mutex mapping_lock;
0472     struct page *ff_page;
0473     bool mmio_err_ff;
0474     bool kernelapi;
0475 
0476     spinlock_t sste_lock; /* Protects segment table entries */
0477     struct cxl_sste *sstp;
0478     u64 sstp0, sstp1;
0479     unsigned int sst_size, sst_lru;
0480 
0481     wait_queue_head_t wq;
0482     /* pid of the group leader associated with the pid */
0483     struct pid *glpid;
0484     /* use mm context associated with this pid for ds faults */
0485     struct pid *pid;
0486     spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
0487     /* Only used in PR mode */
0488     u64 process_token;
0489 
0490     /* driver private data */
0491     void *priv;
0492 
0493     unsigned long *irq_bitmap; /* Accessed from IRQ context */
0494     struct cxl_irq_ranges irqs;
0495     struct list_head irq_names;
0496     u64 fault_addr;
0497     u64 fault_dsisr;
0498     u64 afu_err;
0499 
0500     /*
0501      * This status and it's lock pretects start and detach context
0502      * from racing.  It also prevents detach from racing with
0503      * itself
0504      */
0505     enum cxl_context_status status;
0506     struct mutex status_mutex;
0507 
0508 
0509     /* XXX: Is it possible to need multiple work items at once? */
0510     struct work_struct fault_work;
0511     u64 dsisr;
0512     u64 dar;
0513 
0514     struct cxl_process_element *elem;
0515 
0516     /*
0517      * pe is the process element handle, assigned by this driver when the
0518      * context is initialized.
0519      *
0520      * external_pe is the PE shown outside of cxl.
0521      * On bare-metal, pe=external_pe, because we decide what the handle is.
0522      * In a guest, we only find out about the pe used by pHyp when the
0523      * context is attached, and that's the value we want to report outside
0524      * of cxl.
0525      */
0526     int pe;
0527     int external_pe;
0528 
0529     u32 irq_count;
0530     bool pe_inserted;
0531     bool master;
0532     bool kernel;
0533     bool real_mode;
0534     bool pending_irq;
0535     bool pending_fault;
0536     bool pending_afu_err;
0537 
0538     /* Used by AFU drivers for driver specific event delivery */
0539     struct cxl_afu_driver_ops *afu_driver_ops;
0540     atomic_t afu_driver_events;
0541 
0542     struct rcu_head rcu;
0543 
0544     /*
0545      * Only used when more interrupts are allocated via
0546      * pci_enable_msix_range than are supported in the default context, to
0547      * use additional contexts to overcome the limitation. i.e. Mellanox
0548      * CX4 only:
0549      */
0550     struct list_head extra_irq_contexts;
0551 };
0552 
0553 struct cxl_service_layer_ops {
0554     int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
0555     int (*afu_regs_init)(struct cxl_afu *afu);
0556     int (*register_serr_irq)(struct cxl_afu *afu);
0557     void (*release_serr_irq)(struct cxl_afu *afu);
0558     void (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir);
0559     void (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir);
0560     void (*psl_irq_dump_registers)(struct cxl_context *ctx);
0561     void (*err_irq_dump_registers)(struct cxl *adapter);
0562     void (*debugfs_stop_trace)(struct cxl *adapter);
0563     void (*write_timebase_ctrl)(struct cxl *adapter);
0564     u64 (*timebase_read)(struct cxl *adapter);
0565     int capi_mode;
0566     bool needs_reset_before_disable;
0567 };
0568 
0569 struct cxl_native {
0570     u64 afu_desc_off;
0571     u64 afu_desc_size;
0572     void __iomem *p1_mmio;
0573     void __iomem *p2_mmio;
0574     irq_hw_number_t err_hwirq;
0575     unsigned int err_virq;
0576     u64 ps_off;
0577     const struct cxl_service_layer_ops *sl_ops;
0578 };
0579 
0580 struct cxl_guest {
0581     struct platform_device *pdev;
0582     int irq_nranges;
0583     struct cdev cdev;
0584     irq_hw_number_t irq_base_offset;
0585     struct irq_avail *irq_avail;
0586     spinlock_t irq_alloc_lock;
0587     u64 handle;
0588     char *status;
0589     u16 vendor;
0590     u16 device;
0591     u16 subsystem_vendor;
0592     u16 subsystem;
0593 };
0594 
0595 struct cxl {
0596     struct cxl_native *native;
0597     struct cxl_guest *guest;
0598     spinlock_t afu_list_lock;
0599     struct cxl_afu *afu[CXL_MAX_SLICES];
0600     struct device dev;
0601     struct dentry *trace;
0602     struct dentry *psl_err_chk;
0603     struct dentry *debugfs;
0604     char *irq_name;
0605     struct bin_attribute cxl_attr;
0606     int adapter_num;
0607     int user_irqs;
0608     int min_pe;
0609     u64 ps_size;
0610     u16 psl_rev;
0611     u16 base_image;
0612     u8 vsec_status;
0613     u8 caia_major;
0614     u8 caia_minor;
0615     u8 slices;
0616     bool user_image_loaded;
0617     bool perst_loads_image;
0618     bool perst_select_user;
0619     bool perst_same_image;
0620     bool psl_timebase_synced;
0621 
0622     /*
0623      * number of contexts mapped on to this card. Possible values are:
0624      * >0: Number of contexts mapped and new one can be mapped.
0625      *  0: No active contexts and new ones can be mapped.
0626      * -1: No contexts mapped and new ones cannot be mapped.
0627      */
0628     atomic_t contexts_num;
0629 };
0630 
0631 int cxl_pci_alloc_one_irq(struct cxl *adapter);
0632 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
0633 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
0634 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
0635 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
0636 int cxl_update_image_control(struct cxl *adapter);
0637 int cxl_pci_reset(struct cxl *adapter);
0638 void cxl_pci_release_afu(struct device *dev);
0639 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
0640 
0641 /* common == phyp + powernv */
0642 struct cxl_process_element_common {
0643     __be32 tid;
0644     __be32 pid;
0645     __be64 csrp;
0646     __be64 aurp0;
0647     __be64 aurp1;
0648     __be64 sstp0;
0649     __be64 sstp1;
0650     __be64 amr;
0651     u8     reserved3[4];
0652     __be64 wed;
0653 } __packed;
0654 
0655 /* just powernv */
0656 struct cxl_process_element {
0657     __be64 sr;
0658     __be64 SPOffset;
0659     __be64 sdr;
0660     __be64 haurp;
0661     __be32 ctxtime;
0662     __be16 ivte_offsets[4];
0663     __be16 ivte_ranges[4];
0664     __be32 lpid;
0665     struct cxl_process_element_common common;
0666     __be32 software_state;
0667 } __packed;
0668 
0669 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
0670 {
0671     struct pci_dev *pdev;
0672 
0673     if (cpu_has_feature(CPU_FTR_HVMODE)) {
0674         pdev = to_pci_dev(cxl->dev.parent);
0675         return !pci_channel_offline(pdev);
0676     }
0677     return true;
0678 }
0679 
0680 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
0681 {
0682     WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
0683     return cxl->native->p1_mmio + cxl_reg_off(reg);
0684 }
0685 
0686 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
0687 {
0688     if (likely(cxl_adapter_link_ok(cxl, NULL)))
0689         out_be64(_cxl_p1_addr(cxl, reg), val);
0690 }
0691 
0692 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
0693 {
0694     if (likely(cxl_adapter_link_ok(cxl, NULL)))
0695         return in_be64(_cxl_p1_addr(cxl, reg));
0696     else
0697         return ~0ULL;
0698 }
0699 
0700 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
0701 {
0702     WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
0703     return afu->native->p1n_mmio + cxl_reg_off(reg);
0704 }
0705 
0706 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
0707 {
0708     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0709         out_be64(_cxl_p1n_addr(afu, reg), val);
0710 }
0711 
0712 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
0713 {
0714     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0715         return in_be64(_cxl_p1n_addr(afu, reg));
0716     else
0717         return ~0ULL;
0718 }
0719 
0720 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
0721 {
0722     return afu->p2n_mmio + cxl_reg_off(reg);
0723 }
0724 
0725 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
0726 {
0727     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0728         out_be64(_cxl_p2n_addr(afu, reg), val);
0729 }
0730 
0731 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
0732 {
0733     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0734         return in_be64(_cxl_p2n_addr(afu, reg));
0735     else
0736         return ~0ULL;
0737 }
0738 
0739 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
0740                 loff_t off, size_t count);
0741 
0742 /* Internal functions wrapped in cxl_base to allow PHB to call them */
0743 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
0744 void _cxl_pci_disable_device(struct pci_dev *dev);
0745 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
0746 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
0747 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
0748 
0749 struct cxl_calls {
0750     void (*cxl_slbia)(struct mm_struct *mm);
0751     bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
0752     void (*cxl_pci_disable_device)(struct pci_dev *dev);
0753     int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
0754     int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
0755     void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
0756 
0757     struct module *owner;
0758 };
0759 int register_cxl_calls(struct cxl_calls *calls);
0760 void unregister_cxl_calls(struct cxl_calls *calls);
0761 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
0762 
0763 void cxl_remove_adapter_nr(struct cxl *adapter);
0764 
0765 int cxl_alloc_spa(struct cxl_afu *afu);
0766 void cxl_release_spa(struct cxl_afu *afu);
0767 
0768 dev_t cxl_get_dev(void);
0769 int cxl_file_init(void);
0770 void cxl_file_exit(void);
0771 int cxl_register_adapter(struct cxl *adapter);
0772 int cxl_register_afu(struct cxl_afu *afu);
0773 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
0774 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
0775 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
0776 void cxl_chardev_afu_remove(struct cxl_afu *afu);
0777 
0778 void cxl_context_detach_all(struct cxl_afu *afu);
0779 void cxl_context_free(struct cxl_context *ctx);
0780 void cxl_context_detach(struct cxl_context *ctx);
0781 
0782 int cxl_sysfs_adapter_add(struct cxl *adapter);
0783 void cxl_sysfs_adapter_remove(struct cxl *adapter);
0784 int cxl_sysfs_afu_add(struct cxl_afu *afu);
0785 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
0786 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
0787 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
0788 
0789 struct cxl *cxl_alloc_adapter(void);
0790 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
0791 int cxl_afu_select_best_mode(struct cxl_afu *afu);
0792 
0793 int cxl_native_register_psl_irq(struct cxl_afu *afu);
0794 void cxl_native_release_psl_irq(struct cxl_afu *afu);
0795 int cxl_native_register_psl_err_irq(struct cxl *adapter);
0796 void cxl_native_release_psl_err_irq(struct cxl *adapter);
0797 int cxl_native_register_serr_irq(struct cxl_afu *afu);
0798 void cxl_native_release_serr_irq(struct cxl_afu *afu);
0799 int afu_register_irqs(struct cxl_context *ctx, u32 count);
0800 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
0801 void afu_irq_name_free(struct cxl_context *ctx);
0802 
0803 int cxl_debugfs_init(void);
0804 void cxl_debugfs_exit(void);
0805 int cxl_debugfs_adapter_add(struct cxl *adapter);
0806 void cxl_debugfs_adapter_remove(struct cxl *adapter);
0807 int cxl_debugfs_afu_add(struct cxl_afu *afu);
0808 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
0809 
0810 void cxl_handle_fault(struct work_struct *work);
0811 void cxl_prefault(struct cxl_context *ctx, u64 wed);
0812 
0813 struct cxl *get_cxl_adapter(int num);
0814 int cxl_alloc_sst(struct cxl_context *ctx);
0815 void cxl_dump_debug_buffer(void *addr, size_t size);
0816 
0817 void init_cxl_native(void);
0818 
0819 struct cxl_context *cxl_context_alloc(void);
0820 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
0821 void cxl_context_set_mapping(struct cxl_context *ctx,
0822             struct address_space *mapping);
0823 void cxl_context_free(struct cxl_context *ctx);
0824 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
0825 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
0826              irq_handler_t handler, void *cookie, const char *name);
0827 void cxl_unmap_irq(unsigned int virq, void *cookie);
0828 int __detach_context(struct cxl_context *ctx);
0829 
0830 /*
0831  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
0832  * in PAPR.
0833  * A word about endianness: a pointer to this structure is passed when
0834  * calling the hcall. However, it is not a block of memory filled up by
0835  * the hypervisor. The return values are found in registers, and copied
0836  * one by one when returning from the hcall. See the end of the call to
0837  * plpar_hcall9() in hvCall.S
0838  * As a consequence:
0839  * - we don't need to do any endianness conversion
0840  * - the pid and tid are an exception. They are 32-bit values returned in
0841  *   the same 64-bit register. So we do need to worry about byte ordering.
0842  */
0843 struct cxl_irq_info {
0844     u64 dsisr;
0845     u64 dar;
0846     u64 dsr;
0847 #ifndef CONFIG_CPU_LITTLE_ENDIAN
0848     u32 pid;
0849     u32 tid;
0850 #else
0851     u32 tid;
0852     u32 pid;
0853 #endif
0854     u64 afu_err;
0855     u64 errstat;
0856     u64 proc_handle;
0857     u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
0858 };
0859 
0860 void cxl_assign_psn_space(struct cxl_context *ctx);
0861 irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
0862 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
0863             void *cookie, irq_hw_number_t *dest_hwirq,
0864             unsigned int *dest_virq, const char *name);
0865 
0866 int cxl_check_error(struct cxl_afu *afu);
0867 int cxl_afu_slbia(struct cxl_afu *afu);
0868 int cxl_tlb_slb_invalidate(struct cxl *adapter);
0869 int cxl_data_cache_flush(struct cxl *adapter);
0870 int cxl_afu_disable(struct cxl_afu *afu);
0871 int cxl_psl_purge(struct cxl_afu *afu);
0872 
0873 void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir);
0874 void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir);
0875 void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir);
0876 void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx);
0877 void cxl_native_err_irq_dump_regs(struct cxl *adapter);
0878 void cxl_stop_trace(struct cxl *cxl);
0879 int cxl_pci_vphb_add(struct cxl_afu *afu);
0880 void cxl_pci_vphb_remove(struct cxl_afu *afu);
0881 void cxl_release_mapping(struct cxl_context *ctx);
0882 
0883 extern struct pci_driver cxl_pci_driver;
0884 extern struct platform_driver cxl_of_driver;
0885 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
0886 
0887 int afu_open(struct inode *inode, struct file *file);
0888 int afu_release(struct inode *inode, struct file *file);
0889 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
0890 int afu_mmap(struct file *file, struct vm_area_struct *vm);
0891 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
0892 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
0893 extern const struct file_operations afu_fops;
0894 
0895 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
0896 void cxl_guest_remove_adapter(struct cxl *adapter);
0897 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
0898 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
0899 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
0900 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
0901 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
0902 void cxl_guest_remove_afu(struct cxl_afu *afu);
0903 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
0904 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
0905 int cxl_guest_add_chardev(struct cxl *adapter);
0906 void cxl_guest_remove_chardev(struct cxl *adapter);
0907 void cxl_guest_reload_module(struct cxl *adapter);
0908 int cxl_of_probe(struct platform_device *pdev);
0909 
0910 struct cxl_backend_ops {
0911     struct module *module;
0912     int (*adapter_reset)(struct cxl *adapter);
0913     int (*alloc_one_irq)(struct cxl *adapter);
0914     void (*release_one_irq)(struct cxl *adapter, int hwirq);
0915     int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
0916                 struct cxl *adapter, unsigned int num);
0917     void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
0918                 struct cxl *adapter);
0919     int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
0920             unsigned int virq);
0921     irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
0922                     u64 dsisr, u64 errstat);
0923     irqreturn_t (*psl_interrupt)(int irq, void *data);
0924     int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
0925     void (*irq_wait)(struct cxl_context *ctx);
0926     int (*attach_process)(struct cxl_context *ctx, bool kernel,
0927             u64 wed, u64 amr);
0928     int (*detach_process)(struct cxl_context *ctx);
0929     void (*update_ivtes)(struct cxl_context *ctx);
0930     bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
0931     bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
0932     void (*release_afu)(struct device *dev);
0933     ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
0934                 loff_t off, size_t count);
0935     int (*afu_check_and_enable)(struct cxl_afu *afu);
0936     int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
0937     int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
0938     int (*afu_reset)(struct cxl_afu *afu);
0939     int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
0940     int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
0941     int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
0942     int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
0943     int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
0944     int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
0945     int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
0946     ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
0947 };
0948 extern const struct cxl_backend_ops cxl_native_ops;
0949 extern const struct cxl_backend_ops cxl_guest_ops;
0950 extern const struct cxl_backend_ops *cxl_ops;
0951 
0952 /* check if the given pci_dev is on the the cxl vphb bus */
0953 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
0954 
0955 /* decode AFU error bits in the PSL register PSL_SERR_An */
0956 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
0957 
0958 /*
0959  * Increments the number of attached contexts on an adapter.
0960  * In case an adapter_context_lock is taken the return -EBUSY.
0961  */
0962 int cxl_adapter_context_get(struct cxl *adapter);
0963 
0964 /* Decrements the number of attached contexts on an adapter */
0965 void cxl_adapter_context_put(struct cxl *adapter);
0966 
0967 /* If no active contexts then prevents contexts from being attached */
0968 int cxl_adapter_context_lock(struct cxl *adapter);
0969 
0970 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
0971 void cxl_adapter_context_unlock(struct cxl *adapter);
0972 
0973 #endif