Back to home page

LXR

 
 

    


0001 /*
0002  * Copyright 2011 Tilera Corporation. All Rights Reserved.
0003  *
0004  *   This program is free software; you can redistribute it and/or
0005  *   modify it under the terms of the GNU General Public License
0006  *   as published by the Free Software Foundation, version 2.
0007  *
0008  *   This program is distributed in the hope that it will be useful, but
0009  *   WITHOUT ANY WARRANTY; without even the implied warranty of
0010  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
0011  *   NON INFRINGEMENT.  See the GNU General Public License for
0012  *   more details.
0013  */
0014 
0015 #include <linux/linkage.h>
0016 #include <asm/ptrace.h>
0017 #include <asm/asm-offsets.h>
0018 #include <arch/spr_def.h>
0019 #include <asm/processor.h>
0020 #include <asm/switch_to.h>
0021 
0022 /*
0023  * See <asm/switch_to.h>; called with prev and next task_struct pointers.
0024  * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
0025  *
0026  * We want to save pc/sp in "prev", and get the new pc/sp from "next".
0027  * We also need to save all the callee-saved registers on the stack.
0028  *
0029  * Intel enables/disables access to the hardware cycle counter in
0030  * seccomp (secure computing) environments if necessary, based on
0031  * has_secure_computing().  We might want to do this at some point,
0032  * though it would require virtualizing the other SPRs under WORLD_ACCESS.
0033  *
0034  * Since we're saving to the stack, we omit sp from this list.
0035  * And for parallels with other architectures, we save lr separately,
0036  * in the thread_struct itself (as the "pc" field).
0037  *
0038  * This code also needs to be aligned with process.c copy_thread()
0039  */
0040 
0041 #if CALLEE_SAVED_REGS_COUNT != 24
0042 # error Mismatch between <asm/switch_to.h> and kernel/entry.S
0043 #endif
0044 #define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
0045 
0046 #define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
0047 #define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
0048 #define FOR_EACH_CALLEE_SAVED_REG(f)                    \
0049                             f(r30); f(r31); \
0050     f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
0051     f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
0052     f(r48); f(r49); f(r50); f(r51); f(r52);
0053 
0054 STD_ENTRY_SECTION(__switch_to, .sched.text)
0055     {
0056       move r10, sp
0057       st sp, lr
0058     }
0059     {
0060       addli r11, sp, -FRAME_SIZE + 8
0061       addli sp, sp, -FRAME_SIZE
0062     }
0063     {
0064       st r11, r10
0065       addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
0066     }
0067     {
0068       ld r13, r4   /* Load new sp to a temp register early. */
0069       addi r12, sp, 16
0070     }
0071     FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
0072     addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
0073     {
0074       st r3, sp
0075       addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
0076     }
0077     {
0078       st r3, lr
0079       addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
0080     }
0081     {
0082       ld lr, r4
0083       addi r12, r13, 16
0084     }
0085     {
0086       /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
0087       move sp, r13
0088       mtspr SPR_SYSTEM_SAVE_K_0, r2
0089     }
0090     FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
0091 .L__switch_to_pc:
0092     {
0093       addli sp, sp, FRAME_SIZE
0094       jrp lr   /* r0 is still valid here, so return it */
0095     }
0096     STD_ENDPROC(__switch_to)
0097 
0098 /* Return a suitable address for the backtracer for suspended threads */
0099 STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
0100     lnk r0
0101     {
0102       addli r0, r0, .L__switch_to_pc - .
0103       jrp lr
0104     }
0105     STD_ENDPROC(get_switch_to_pc)
0106 
0107 STD_ENTRY(get_pt_regs)
0108     .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
0109          r8, r9, r10, r11, r12, r13, r14, r15, \
0110          r16, r17, r18, r19, r20, r21, r22, r23, \
0111          r24, r25, r26, r27, r28, r29, r30, r31, \
0112          r32, r33, r34, r35, r36, r37, r38, r39, \
0113          r40, r41, r42, r43, r44, r45, r46, r47, \
0114          r48, r49, r50, r51, r52, tp, sp
0115     {
0116      st r0, \reg
0117      addi r0, r0, 8
0118     }
0119     .endr
0120     {
0121      st r0, lr
0122      addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
0123     }
0124     lnk r1
0125     {
0126      st r0, r1
0127      addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
0128     }
0129     mfspr r1, INTERRUPT_CRITICAL_SECTION
0130     shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
0131     ori r1, r1, KERNEL_PL
0132     {
0133      st r0, r1
0134      addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
0135     }
0136     {
0137      st r0, zero       /* clear faultnum */
0138      addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
0139     }
0140     {
0141      st r0, zero       /* clear orig_r0 */
0142      addli r0, r0, -PTREGS_OFFSET_ORIG_R0    /* restore r0 to base */
0143     }
0144     jrp lr
0145     STD_ENDPROC(get_pt_regs)