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0001 /*
0002  * OpenRISC head.S
0003  *
0004  * Linux architectural port borrowing liberally from similar works of
0005  * others.  All original copyrights apply as per the original source
0006  * declaration.
0007  *
0008  * Modifications for the OpenRISC architecture:
0009  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
0010  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
0011  *
0012  *      This program is free software; you can redistribute it and/or
0013  *      modify it under the terms of the GNU General Public License
0014  *      as published by the Free Software Foundation; either version
0015  *      2 of the License, or (at your option) any later version.
0016  */
0017 
0018 #include <linux/linkage.h>
0019 #include <linux/threads.h>
0020 #include <linux/errno.h>
0021 #include <linux/init.h>
0022 #include <linux/serial_reg.h>
0023 #include <asm/processor.h>
0024 #include <asm/page.h>
0025 #include <asm/mmu.h>
0026 #include <asm/pgtable.h>
0027 #include <asm/cache.h>
0028 #include <asm/spr_defs.h>
0029 #include <asm/asm-offsets.h>
0030 #include <linux/of_fdt.h>
0031 
0032 #define tophys(rd,rs)               \
0033     l.movhi rd,hi(-KERNELBASE)      ;\
0034     l.add   rd,rd,rs
0035 
0036 #define CLEAR_GPR(gpr)              \
0037     l.or    gpr,r0,r0
0038 
0039 #define LOAD_SYMBOL_2_GPR(gpr,symbol)       \
0040     l.movhi gpr,hi(symbol)          ;\
0041     l.ori   gpr,gpr,lo(symbol)
0042 
0043 
0044 #define UART_BASE_ADD      0x90000000
0045 
0046 #define EXCEPTION_SR  (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
0047 #define SYSCALL_SR  (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
0048 
0049 /* ============================================[ tmp store locations ]=== */
0050 
0051 /*
0052  * emergency_print temporary stores
0053  */
0054 #define EMERGENCY_PRINT_STORE_GPR4  l.sw    0x20(r0),r4
0055 #define EMERGENCY_PRINT_LOAD_GPR4   l.lwz   r4,0x20(r0)
0056 
0057 #define EMERGENCY_PRINT_STORE_GPR5  l.sw    0x24(r0),r5
0058 #define EMERGENCY_PRINT_LOAD_GPR5   l.lwz   r5,0x24(r0)
0059 
0060 #define EMERGENCY_PRINT_STORE_GPR6  l.sw    0x28(r0),r6
0061 #define EMERGENCY_PRINT_LOAD_GPR6   l.lwz   r6,0x28(r0)
0062 
0063 #define EMERGENCY_PRINT_STORE_GPR7  l.sw    0x2c(r0),r7
0064 #define EMERGENCY_PRINT_LOAD_GPR7   l.lwz   r7,0x2c(r0)
0065 
0066 #define EMERGENCY_PRINT_STORE_GPR8  l.sw    0x30(r0),r8
0067 #define EMERGENCY_PRINT_LOAD_GPR8   l.lwz   r8,0x30(r0)
0068 
0069 #define EMERGENCY_PRINT_STORE_GPR9  l.sw    0x34(r0),r9
0070 #define EMERGENCY_PRINT_LOAD_GPR9   l.lwz   r9,0x34(r0)
0071 
0072 
0073 /*
0074  * TLB miss handlers temorary stores
0075  */
0076 #define EXCEPTION_STORE_GPR9        l.sw    0x10(r0),r9
0077 #define EXCEPTION_LOAD_GPR9     l.lwz   r9,0x10(r0)
0078 
0079 #define EXCEPTION_STORE_GPR2        l.sw    0x64(r0),r2
0080 #define EXCEPTION_LOAD_GPR2     l.lwz   r2,0x64(r0)
0081 
0082 #define EXCEPTION_STORE_GPR3        l.sw    0x68(r0),r3
0083 #define EXCEPTION_LOAD_GPR3     l.lwz   r3,0x68(r0)
0084 
0085 #define EXCEPTION_STORE_GPR4        l.sw    0x6c(r0),r4
0086 #define EXCEPTION_LOAD_GPR4     l.lwz   r4,0x6c(r0)
0087 
0088 #define EXCEPTION_STORE_GPR5        l.sw    0x70(r0),r5
0089 #define EXCEPTION_LOAD_GPR5     l.lwz   r5,0x70(r0)
0090 
0091 #define EXCEPTION_STORE_GPR6        l.sw    0x74(r0),r6
0092 #define EXCEPTION_LOAD_GPR6     l.lwz   r6,0x74(r0)
0093 
0094 
0095 /*
0096  * EXCEPTION_HANDLE temporary stores
0097  */
0098 
0099 #define EXCEPTION_T_STORE_GPR30     l.sw    0x78(r0),r30
0100 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz   reg,0x78(r0)
0101 
0102 #define EXCEPTION_T_STORE_GPR10     l.sw    0x7c(r0),r10
0103 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz   reg,0x7c(r0)
0104 
0105 #define EXCEPTION_T_STORE_SP        l.sw    0x80(r0),r1
0106 #define EXCEPTION_T_LOAD_SP(reg)    l.lwz   reg,0x80(r0)
0107 
0108 /*
0109  * For UNHANLDED_EXCEPTION
0110  */
0111 
0112 #define EXCEPTION_T_STORE_GPR31     l.sw    0x84(r0),r31
0113 #define EXCEPTION_T_LOAD_GPR31(reg) l.lwz   reg,0x84(r0)
0114 
0115 /* =========================================================[ macros ]=== */
0116 
0117 
0118 #define GET_CURRENT_PGD(reg,t1)                 \
0119     LOAD_SYMBOL_2_GPR(reg,current_pgd)          ;\
0120     tophys  (t1,reg)                    ;\
0121     l.lwz   reg,0(t1)
0122 
0123 
0124 /*
0125  * DSCR: this is a common hook for handling exceptions. it will save
0126  *       the needed registers, set up stack and pointer to current
0127  *   then jump to the handler while enabling MMU
0128  *
0129  * PRMS: handler    - a function to jump to. it has to save the
0130  *          remaining registers to kernel stack, call
0131  *          appropriate arch-independant exception handler
0132  *          and finaly jump to ret_from_except
0133  *
0134  * PREQ: unchanged state from the time exception happened
0135  *
0136  * POST: SAVED the following registers original value
0137  *         to the new created exception frame pointed to by r1
0138  *
0139  *   r1  - ksp  pointing to the new (exception) frame
0140  *   r4  - EEAR     exception EA
0141  *   r10 - current  pointing to current_thread_info struct
0142  *   r12 - syscall  0, since we didn't come from syscall
0143  *   r13 - temp it actually contains new SR, not needed anymore
0144  *   r31 - handler  address of the handler we'll jump to
0145  *
0146  *   handler has to save remaining registers to the exception
0147  *   ksp frame *before* tainting them!
0148  *
0149  * NOTE: this function is not reentrant per se. reentrancy is guaranteed
0150  *       by processor disabling all exceptions/interrupts when exception
0151  *   accours.
0152  *
0153  * OPTM: no need to make it so wasteful to extract ksp when in user mode
0154  */
0155 
0156 #define EXCEPTION_HANDLE(handler)               \
0157     EXCEPTION_T_STORE_GPR30                 ;\
0158     l.mfspr r30,r0,SPR_ESR_BASE             ;\
0159     l.andi  r30,r30,SPR_SR_SM               ;\
0160     l.sfeqi r30,0                       ;\
0161     EXCEPTION_T_STORE_GPR10                 ;\
0162     l.bnf   2f                            /* kernel_mode */ ;\
0163      EXCEPTION_T_STORE_SP                 /* delay slot */  ;\
0164 1: /* user_mode:   */                       ;\
0165     LOAD_SYMBOL_2_GPR(r1,current_thread_info_set)       ;\
0166     tophys  (r30,r1)                    ;\
0167     /* r10: current_thread_info  */             ;\
0168     l.lwz   r10,0(r30)                  ;\
0169     tophys  (r30,r10)                   ;\
0170     l.lwz   r1,(TI_KSP)(r30)                ;\
0171     /* fall through */                  ;\
0172 2: /* kernel_mode: */                       ;\
0173     /* create new stack frame, save only needed gprs */ ;\
0174     /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */   ;\
0175     /* r12: temp, syscall indicator */          ;\
0176     l.addi  r1,r1,-(INT_FRAME_SIZE)             ;\
0177     /* r1 is KSP, r30 is __pa(KSP) */           ;\
0178     tophys  (r30,r1)                    ;\
0179     l.sw    PT_GPR12(r30),r12               ;\
0180     l.mfspr r12,r0,SPR_EPCR_BASE                ;\
0181     l.sw    PT_PC(r30),r12                  ;\
0182     l.mfspr r12,r0,SPR_ESR_BASE             ;\
0183     l.sw    PT_SR(r30),r12                  ;\
0184     /* save r30 */                      ;\
0185     EXCEPTION_T_LOAD_GPR30(r12)             ;\
0186     l.sw    PT_GPR30(r30),r12               ;\
0187     /* save r10 as was prior to exception */        ;\
0188     EXCEPTION_T_LOAD_GPR10(r12)             ;\
0189     l.sw    PT_GPR10(r30),r12               ;\
0190     /* save PT_SP as was prior to exception */      ;\
0191     EXCEPTION_T_LOAD_SP(r12)                ;\
0192     l.sw    PT_SP(r30),r12                  ;\
0193     /* save exception r4, set r4 = EA */            ;\
0194     l.sw    PT_GPR4(r30),r4                 ;\
0195     l.mfspr r4,r0,SPR_EEAR_BASE             ;\
0196     /* r12 == 1 if we come from syscall */          ;\
0197     CLEAR_GPR(r12)                      ;\
0198     /* ----- turn on MMU ----- */               ;\
0199     l.ori   r30,r0,(EXCEPTION_SR)               ;\
0200     l.mtspr r0,r30,SPR_ESR_BASE             ;\
0201     /* r30: EA address of handler */            ;\
0202     LOAD_SYMBOL_2_GPR(r30,handler)              ;\
0203     l.mtspr r0,r30,SPR_EPCR_BASE                ;\
0204     l.rfe
0205 
0206 /*
0207  * this doesn't work
0208  *
0209  *
0210  * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
0211  * #define UNHANDLED_EXCEPTION(handler)             \
0212  *  l.ori   r3,r0,0x1                   ;\
0213  *  l.mtspr r0,r3,SPR_SR                    ;\
0214  *      l.movhi r3,hi(0xf0000100)               ;\
0215  *      l.ori   r3,r3,lo(0xf0000100)                ;\
0216  *  l.jr    r3                      ;\
0217  *  l.nop   1
0218  *
0219  * #endif
0220  */
0221 
0222 /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
0223  *       a bit more carefull (if we have a PT_SP or current pointer
0224  *       corruption) and set them up from 'current_set'
0225  *
0226  */
0227 #define UNHANDLED_EXCEPTION(handler)                \
0228     EXCEPTION_T_STORE_GPR31                 ;\
0229     EXCEPTION_T_STORE_GPR10                 ;\
0230     EXCEPTION_T_STORE_SP                    ;\
0231     /* temporary store r3, r9 into r1, r10 */       ;\
0232     l.addi  r1,r3,0x0                   ;\
0233     l.addi  r10,r9,0x0                  ;\
0234     /* the string referenced by r3 must be low enough */    ;\
0235     l.jal   _emergency_print                ;\
0236     l.ori   r3,r0,lo(_string_unhandled_exception)       ;\
0237     l.mfspr r3,r0,SPR_NPC                   ;\
0238     l.jal   _emergency_print_nr             ;\
0239     l.andi  r3,r3,0x1f00                    ;\
0240     /* the string referenced by r3 must be low enough */    ;\
0241     l.jal   _emergency_print                ;\
0242     l.ori   r3,r0,lo(_string_epc_prefix)            ;\
0243     l.jal   _emergency_print_nr             ;\
0244     l.mfspr r3,r0,SPR_EPCR_BASE             ;\
0245     l.jal   _emergency_print                ;\
0246     l.ori   r3,r0,lo(_string_nl)                ;\
0247     /* end of printing */                   ;\
0248     l.addi  r3,r1,0x0                   ;\
0249     l.addi  r9,r10,0x0                  ;\
0250     /* extract current, ksp from current_set */     ;\
0251     LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top)      ;\
0252     LOAD_SYMBOL_2_GPR(r10,init_thread_union)        ;\
0253     /* create new stack frame, save only needed gprs */ ;\
0254     /* r1: KSP, r10: current, r31: __pa(KSP) */     ;\
0255     /* r12: temp, syscall indicator, r13 temp */        ;\
0256     l.addi  r1,r1,-(INT_FRAME_SIZE)             ;\
0257     /* r1 is KSP, r31 is __pa(KSP) */           ;\
0258     tophys  (r31,r1)                    ;\
0259     l.sw    PT_GPR12(r31),r12                   ;\
0260     l.mfspr r12,r0,SPR_EPCR_BASE                ;\
0261     l.sw    PT_PC(r31),r12                  ;\
0262     l.mfspr r12,r0,SPR_ESR_BASE             ;\
0263     l.sw    PT_SR(r31),r12                  ;\
0264     /* save r31 */                      ;\
0265     EXCEPTION_T_LOAD_GPR31(r12)             ;\
0266     l.sw    PT_GPR31(r31),r12                   ;\
0267     /* save r10 as was prior to exception */        ;\
0268     EXCEPTION_T_LOAD_GPR10(r12)             ;\
0269     l.sw    PT_GPR10(r31),r12                   ;\
0270     /* save PT_SP as was prior to exception */          ;\
0271     EXCEPTION_T_LOAD_SP(r12)                ;\
0272     l.sw    PT_SP(r31),r12                  ;\
0273     l.sw    PT_GPR13(r31),r13                   ;\
0274     /* --> */                       ;\
0275     /* save exception r4, set r4 = EA */            ;\
0276     l.sw    PT_GPR4(r31),r4                 ;\
0277     l.mfspr r4,r0,SPR_EEAR_BASE             ;\
0278     /* r12 == 1 if we come from syscall */          ;\
0279     CLEAR_GPR(r12)                      ;\
0280     /* ----- play a MMU trick ----- */          ;\
0281     l.ori   r31,r0,(EXCEPTION_SR)               ;\
0282     l.mtspr r0,r31,SPR_ESR_BASE             ;\
0283     /* r31: EA address of handler */            ;\
0284     LOAD_SYMBOL_2_GPR(r31,handler)              ;\
0285     l.mtspr r0,r31,SPR_EPCR_BASE                ;\
0286     l.rfe
0287 
0288 /* =====================================================[ exceptions] === */
0289 
0290 /* ---[ 0x100: RESET exception ]----------------------------------------- */
0291     .org 0x100
0292     /* Jump to .init code at _start which lives in the .head section
0293      * and will be discarded after boot.
0294      */
0295     LOAD_SYMBOL_2_GPR(r15, _start)
0296     tophys  (r13,r15)           /* MMU disabled */
0297     l.jr    r13
0298      l.nop
0299 
0300 /* ---[ 0x200: BUS exception ]------------------------------------------- */
0301     .org 0x200
0302 _dispatch_bus_fault:
0303     EXCEPTION_HANDLE(_bus_fault_handler)
0304 
0305 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
0306     .org 0x300
0307 _dispatch_do_dpage_fault:
0308 //      totaly disable timer interrupt
0309 //  l.mtspr r0,r0,SPR_TTMR
0310 //  DEBUG_TLB_PROBE(0x300)
0311 //  EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
0312     EXCEPTION_HANDLE(_data_page_fault_handler)
0313 
0314 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
0315     .org 0x400
0316 _dispatch_do_ipage_fault:
0317 //      totaly disable timer interrupt
0318 //  l.mtspr r0,r0,SPR_TTMR
0319 //  DEBUG_TLB_PROBE(0x400)
0320 //  EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
0321     EXCEPTION_HANDLE(_insn_page_fault_handler)
0322 
0323 /* ---[ 0x500: Timer exception ]----------------------------------------- */
0324     .org 0x500
0325     EXCEPTION_HANDLE(_timer_handler)
0326 
0327 /* ---[ 0x600: Aligment exception ]-------------------------------------- */
0328     .org 0x600
0329     EXCEPTION_HANDLE(_alignment_handler)
0330 
0331 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
0332     .org 0x700
0333     EXCEPTION_HANDLE(_illegal_instruction_handler)
0334 
0335 /* ---[ 0x800: External interrupt exception ]---------------------------- */
0336     .org 0x800
0337     EXCEPTION_HANDLE(_external_irq_handler)
0338 
0339 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
0340     .org 0x900
0341     l.j boot_dtlb_miss_handler
0342     l.nop
0343 
0344 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
0345     .org 0xa00
0346     l.j boot_itlb_miss_handler
0347     l.nop
0348 
0349 /* ---[ 0xb00: Range exception ]----------------------------------------- */
0350     .org 0xb00
0351     UNHANDLED_EXCEPTION(_vector_0xb00)
0352 
0353 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
0354     .org 0xc00
0355     EXCEPTION_HANDLE(_sys_call_handler)
0356 
0357 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
0358     .org 0xd00
0359     UNHANDLED_EXCEPTION(_vector_0xd00)
0360 
0361 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
0362     .org 0xe00
0363 //  UNHANDLED_EXCEPTION(_vector_0xe00)
0364     EXCEPTION_HANDLE(_trap_handler)
0365 
0366 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
0367     .org 0xf00
0368     UNHANDLED_EXCEPTION(_vector_0xf00)
0369 
0370 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
0371     .org 0x1000
0372     UNHANDLED_EXCEPTION(_vector_0x1000)
0373 
0374 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
0375     .org 0x1100
0376     UNHANDLED_EXCEPTION(_vector_0x1100)
0377 
0378 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
0379     .org 0x1200
0380     UNHANDLED_EXCEPTION(_vector_0x1200)
0381 
0382 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
0383     .org 0x1300
0384     UNHANDLED_EXCEPTION(_vector_0x1300)
0385 
0386 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
0387     .org 0x1400
0388     UNHANDLED_EXCEPTION(_vector_0x1400)
0389 
0390 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
0391     .org 0x1500
0392     UNHANDLED_EXCEPTION(_vector_0x1500)
0393 
0394 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
0395     .org 0x1600
0396     UNHANDLED_EXCEPTION(_vector_0x1600)
0397 
0398 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
0399     .org 0x1700
0400     UNHANDLED_EXCEPTION(_vector_0x1700)
0401 
0402 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
0403     .org 0x1800
0404     UNHANDLED_EXCEPTION(_vector_0x1800)
0405 
0406 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
0407     .org 0x1900
0408     UNHANDLED_EXCEPTION(_vector_0x1900)
0409 
0410 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
0411     .org 0x1a00
0412     UNHANDLED_EXCEPTION(_vector_0x1a00)
0413 
0414 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
0415     .org 0x1b00
0416     UNHANDLED_EXCEPTION(_vector_0x1b00)
0417 
0418 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
0419     .org 0x1c00
0420     UNHANDLED_EXCEPTION(_vector_0x1c00)
0421 
0422 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
0423     .org 0x1d00
0424     UNHANDLED_EXCEPTION(_vector_0x1d00)
0425 
0426 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
0427     .org 0x1e00
0428     UNHANDLED_EXCEPTION(_vector_0x1e00)
0429 
0430 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
0431     .org 0x1f00
0432     UNHANDLED_EXCEPTION(_vector_0x1f00)
0433 
0434     .org 0x2000
0435 /* ===================================================[ kernel start ]=== */
0436 
0437 /*    .text*/
0438 
0439 /* This early stuff belongs in HEAD, but some of the functions below definitely
0440  * don't... */
0441 
0442     __HEAD
0443     .global _start
0444 _start:
0445     /* save kernel parameters */
0446     l.or    r25,r0,r3   /* pointer to fdt */
0447 
0448     /*
0449      * ensure a deterministic start
0450      */
0451 
0452     l.ori   r3,r0,0x1
0453     l.mtspr r0,r3,SPR_SR
0454 
0455     CLEAR_GPR(r1)
0456     CLEAR_GPR(r2)
0457     CLEAR_GPR(r3)
0458     CLEAR_GPR(r4)
0459     CLEAR_GPR(r5)
0460     CLEAR_GPR(r6)
0461     CLEAR_GPR(r7)
0462     CLEAR_GPR(r8)
0463     CLEAR_GPR(r9)
0464     CLEAR_GPR(r10)
0465     CLEAR_GPR(r11)
0466     CLEAR_GPR(r12)
0467     CLEAR_GPR(r13)
0468     CLEAR_GPR(r14)
0469     CLEAR_GPR(r15)
0470     CLEAR_GPR(r16)
0471     CLEAR_GPR(r17)
0472     CLEAR_GPR(r18)
0473     CLEAR_GPR(r19)
0474     CLEAR_GPR(r20)
0475     CLEAR_GPR(r21)
0476     CLEAR_GPR(r22)
0477     CLEAR_GPR(r23)
0478     CLEAR_GPR(r24)
0479     CLEAR_GPR(r26)
0480     CLEAR_GPR(r27)
0481     CLEAR_GPR(r28)
0482     CLEAR_GPR(r29)
0483     CLEAR_GPR(r30)
0484     CLEAR_GPR(r31)
0485 
0486     /*
0487      * set up initial ksp and current
0488      */
0489     LOAD_SYMBOL_2_GPR(r1,init_thread_union+0x2000)  // setup kernel stack
0490     LOAD_SYMBOL_2_GPR(r10,init_thread_union)    // setup current
0491     tophys  (r31,r10)
0492     l.sw    TI_KSP(r31), r1
0493 
0494     l.ori   r4,r0,0x0
0495 
0496 
0497     /*
0498      * .data contains initialized data,
0499      * .bss contains uninitialized data - clear it up
0500      */
0501 clear_bss:
0502     LOAD_SYMBOL_2_GPR(r24, __bss_start)
0503     LOAD_SYMBOL_2_GPR(r26, _end)
0504     tophys(r28,r24)
0505     tophys(r30,r26)
0506     CLEAR_GPR(r24)
0507     CLEAR_GPR(r26)
0508 1:
0509     l.sw    (0)(r28),r0
0510     l.sfltu r28,r30
0511     l.bf    1b
0512     l.addi  r28,r28,4
0513 
0514 enable_ic:
0515     l.jal   _ic_enable
0516      l.nop
0517 
0518 enable_dc:
0519     l.jal   _dc_enable
0520      l.nop
0521 
0522 flush_tlb:
0523     /*
0524      *  I N V A L I D A T E   T L B   e n t r i e s
0525      */
0526     LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
0527     LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
0528     l.addi  r7,r0,128 /* Maximum number of sets */
0529 1:
0530     l.mtspr r5,r0,0x0
0531     l.mtspr r6,r0,0x0
0532 
0533     l.addi  r5,r5,1
0534     l.addi  r6,r6,1
0535     l.sfeq  r7,r0
0536     l.bnf   1b
0537      l.addi r7,r7,-1
0538 
0539 
0540 /* The MMU needs to be enabled before or32_early_setup is called */
0541 
0542 enable_mmu:
0543     /*
0544      * enable dmmu & immu
0545      * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
0546      */
0547     l.mfspr r30,r0,SPR_SR
0548     l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
0549     l.ori   r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
0550     l.or    r30,r30,r28
0551     l.mtspr r0,r30,SPR_SR
0552     l.nop
0553     l.nop
0554     l.nop
0555     l.nop
0556     l.nop
0557     l.nop
0558     l.nop
0559     l.nop
0560     l.nop
0561     l.nop
0562     l.nop
0563     l.nop
0564     l.nop
0565     l.nop
0566     l.nop
0567     l.nop
0568 
0569     // reset the simulation counters
0570     l.nop 5
0571 
0572     /* check fdt header magic word */
0573     l.lwz   r3,0(r25)   /* load magic from fdt into r3 */
0574     l.movhi r4,hi(OF_DT_HEADER)
0575     l.ori   r4,r4,lo(OF_DT_HEADER)
0576     l.sfeq  r3,r4
0577     l.bf    _fdt_found
0578      l.nop
0579     /* magic number mismatch, set fdt pointer to null */
0580     l.or    r25,r0,r0
0581 _fdt_found:
0582     /* pass fdt pointer to or32_early_setup in r3 */
0583     l.or    r3,r0,r25
0584     LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
0585     l.jalr r24
0586      l.nop
0587 
0588 clear_regs:
0589     /*
0590      * clear all GPRS to increase determinism
0591      */
0592     CLEAR_GPR(r2)
0593     CLEAR_GPR(r3)
0594     CLEAR_GPR(r4)
0595     CLEAR_GPR(r5)
0596     CLEAR_GPR(r6)
0597     CLEAR_GPR(r7)
0598     CLEAR_GPR(r8)
0599     CLEAR_GPR(r9)
0600     CLEAR_GPR(r11)
0601     CLEAR_GPR(r12)
0602     CLEAR_GPR(r13)
0603     CLEAR_GPR(r14)
0604     CLEAR_GPR(r15)
0605     CLEAR_GPR(r16)
0606     CLEAR_GPR(r17)
0607     CLEAR_GPR(r18)
0608     CLEAR_GPR(r19)
0609     CLEAR_GPR(r20)
0610     CLEAR_GPR(r21)
0611     CLEAR_GPR(r22)
0612     CLEAR_GPR(r23)
0613     CLEAR_GPR(r24)
0614     CLEAR_GPR(r25)
0615     CLEAR_GPR(r26)
0616     CLEAR_GPR(r27)
0617     CLEAR_GPR(r28)
0618     CLEAR_GPR(r29)
0619     CLEAR_GPR(r30)
0620     CLEAR_GPR(r31)
0621 
0622 jump_start_kernel:
0623     /*
0624      * jump to kernel entry (start_kernel)
0625      */
0626     LOAD_SYMBOL_2_GPR(r30, start_kernel)
0627     l.jr    r30
0628      l.nop
0629 
0630 /* ========================================[ cache ]=== */
0631 
0632     /* aligment here so we don't change memory offsets with
0633      * memory controler defined
0634      */
0635     .align 0x2000
0636 
0637 _ic_enable:
0638     /* Check if IC present and skip enabling otherwise */
0639     l.mfspr r24,r0,SPR_UPR
0640     l.andi  r26,r24,SPR_UPR_ICP
0641     l.sfeq  r26,r0
0642     l.bf    9f
0643     l.nop
0644 
0645     /* Disable IC */
0646     l.mfspr r6,r0,SPR_SR
0647     l.addi  r5,r0,-1
0648     l.xori  r5,r5,SPR_SR_ICE
0649     l.and   r5,r6,r5
0650     l.mtspr r0,r5,SPR_SR
0651 
0652     /* Establish cache block size
0653        If BS=0, 16;
0654        If BS=1, 32;
0655        r14 contain block size
0656     */
0657     l.mfspr r24,r0,SPR_ICCFGR
0658     l.andi  r26,r24,SPR_ICCFGR_CBS
0659     l.srli  r28,r26,7
0660     l.ori   r30,r0,16
0661     l.sll   r14,r30,r28
0662 
0663     /* Establish number of cache sets
0664        r16 contains number of cache sets
0665        r28 contains log(# of cache sets)
0666     */
0667     l.andi  r26,r24,SPR_ICCFGR_NCS
0668     l.srli  r28,r26,3
0669     l.ori   r30,r0,1
0670     l.sll   r16,r30,r28
0671 
0672     /* Invalidate IC */
0673     l.addi  r6,r0,0
0674     l.sll   r5,r14,r28
0675 //        l.mul   r5,r14,r16
0676 //  l.trap  1
0677 //  l.addi  r5,r0,IC_SIZE
0678 1:
0679     l.mtspr r0,r6,SPR_ICBIR
0680     l.sfne  r6,r5
0681     l.bf    1b
0682     l.add   r6,r6,r14
0683  //       l.addi   r6,r6,IC_LINE
0684 
0685     /* Enable IC */
0686     l.mfspr r6,r0,SPR_SR
0687     l.ori   r6,r6,SPR_SR_ICE
0688     l.mtspr r0,r6,SPR_SR
0689     l.nop
0690     l.nop
0691     l.nop
0692     l.nop
0693     l.nop
0694     l.nop
0695     l.nop
0696     l.nop
0697     l.nop
0698     l.nop
0699 9:
0700     l.jr    r9
0701     l.nop
0702 
0703 _dc_enable:
0704     /* Check if DC present and skip enabling otherwise */
0705     l.mfspr r24,r0,SPR_UPR
0706     l.andi  r26,r24,SPR_UPR_DCP
0707     l.sfeq  r26,r0
0708     l.bf    9f
0709     l.nop
0710 
0711     /* Disable DC */
0712     l.mfspr r6,r0,SPR_SR
0713     l.addi  r5,r0,-1
0714     l.xori  r5,r5,SPR_SR_DCE
0715     l.and   r5,r6,r5
0716     l.mtspr r0,r5,SPR_SR
0717 
0718     /* Establish cache block size
0719        If BS=0, 16;
0720        If BS=1, 32;
0721        r14 contain block size
0722     */
0723     l.mfspr r24,r0,SPR_DCCFGR
0724     l.andi  r26,r24,SPR_DCCFGR_CBS
0725     l.srli  r28,r26,7
0726     l.ori   r30,r0,16
0727     l.sll   r14,r30,r28
0728 
0729     /* Establish number of cache sets
0730        r16 contains number of cache sets
0731        r28 contains log(# of cache sets)
0732     */
0733     l.andi  r26,r24,SPR_DCCFGR_NCS
0734     l.srli  r28,r26,3
0735     l.ori   r30,r0,1
0736     l.sll   r16,r30,r28
0737 
0738     /* Invalidate DC */
0739     l.addi  r6,r0,0
0740     l.sll   r5,r14,r28
0741 1:
0742     l.mtspr r0,r6,SPR_DCBIR
0743     l.sfne  r6,r5
0744     l.bf    1b
0745     l.add   r6,r6,r14
0746 
0747     /* Enable DC */
0748     l.mfspr r6,r0,SPR_SR
0749     l.ori   r6,r6,SPR_SR_DCE
0750     l.mtspr r0,r6,SPR_SR
0751 9:
0752     l.jr    r9
0753     l.nop
0754 
0755 /* ===============================================[ page table masks ]=== */
0756 
0757 #define DTLB_UP_CONVERT_MASK  0x3fa
0758 #define ITLB_UP_CONVERT_MASK  0x3a
0759 
0760 /* for SMP we'd have (this is a bit subtle, CC must be always set
0761  * for SMP, but since we have _PAGE_PRESENT bit always defined
0762  * we can just modify the mask)
0763  */
0764 #define DTLB_SMP_CONVERT_MASK  0x3fb
0765 #define ITLB_SMP_CONVERT_MASK  0x3b
0766 
0767 /* ---[ boot dtlb miss handler ]----------------------------------------- */
0768 
0769 boot_dtlb_miss_handler:
0770 
0771 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
0772  *                            - (31-12) sets bits belonging to VPN (31-12)
0773  */
0774 #define DTLB_MR_MASK 0xfffff001
0775 
0776 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
0777  *                - (4) sets A (access) bit,
0778  *                            - (5) sets D (dirty) bit,
0779  *                            - (8) sets SRE (superuser read) bit
0780  *                            - (9) sets SWE (superuser write) bit
0781  *                            - (31-12) sets bits belonging to VPN (31-12)
0782  */
0783 #define DTLB_TR_MASK 0xfffff332
0784 
0785 /* These are for masking out the VPN/PPN value from the MR/TR registers...
0786  * it's not the same as the PFN */
0787 #define VPN_MASK 0xfffff000
0788 #define PPN_MASK 0xfffff000
0789 
0790 
0791     EXCEPTION_STORE_GPR6
0792 
0793 #if 0
0794     l.mfspr r6,r0,SPR_ESR_BASE     //
0795     l.andi  r6,r6,SPR_SR_SM            // are we in kernel mode ?
0796     l.sfeqi r6,0                       // r6 == 0x1 --> SM
0797     l.bf    exit_with_no_dtranslation  //
0798     l.nop
0799 #endif
0800 
0801     /* this could be optimized by moving storing of
0802      * non r6 registers here, and jumping r6 restore
0803      * if not in supervisor mode
0804      */
0805 
0806     EXCEPTION_STORE_GPR2
0807     EXCEPTION_STORE_GPR3
0808     EXCEPTION_STORE_GPR4
0809     EXCEPTION_STORE_GPR5
0810 
0811     l.mfspr r4,r0,SPR_EEAR_BASE        // get the offending EA
0812 
0813 immediate_translation:
0814     CLEAR_GPR(r6)
0815 
0816     l.srli  r3,r4,0xd                  // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
0817 
0818     l.mfspr r6, r0, SPR_DMMUCFGR
0819     l.andi  r6, r6, SPR_DMMUCFGR_NTS
0820     l.srli  r6, r6, SPR_DMMUCFGR_NTS_OFF
0821     l.ori   r5, r0, 0x1
0822     l.sll   r5, r5, r6  // r5 = number DMMU sets
0823     l.addi  r6, r5, -1      // r6 = nsets mask
0824     l.and   r2, r3, r6  // r2 <- r3 % NSETS_MASK
0825 
0826     l.or    r6,r6,r4                   // r6 <- r4
0827     l.ori   r6,r6,~(VPN_MASK)          // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
0828     l.movhi r5,hi(DTLB_MR_MASK)        // r5 <- ffff:0000.x000
0829     l.ori   r5,r5,lo(DTLB_MR_MASK)     // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
0830     l.and   r5,r5,r6                   // r5 <- VPN :VPN .x001 - we have DTLBMR entry
0831     l.mtspr r2,r5,SPR_DTLBMR_BASE(0)   // set DTLBMR
0832 
0833     /* set up DTLB with no translation for EA <= 0xbfffffff */
0834     LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
0835     l.sfgeu  r6,r4                     // flag if r6 >= r4 (if 0xbfffffff >= EA)
0836     l.bf     1f                        // goto out
0837     l.and    r3,r4,r4                  // delay slot :: 24 <- r4 (if flag==1)
0838 
0839     tophys(r3,r4)                      // r3 <- PA
0840 1:
0841     l.ori   r3,r3,~(PPN_MASK)          // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
0842     l.movhi r5,hi(DTLB_TR_MASK)        // r5 <- ffff:0000.x000
0843     l.ori   r5,r5,lo(DTLB_TR_MASK)     // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
0844     l.and   r5,r5,r3                   // r5 <- PPN :PPN .x330 - we have DTLBTR entry
0845     l.mtspr r2,r5,SPR_DTLBTR_BASE(0)   // set DTLBTR
0846 
0847     EXCEPTION_LOAD_GPR6
0848     EXCEPTION_LOAD_GPR5
0849     EXCEPTION_LOAD_GPR4
0850     EXCEPTION_LOAD_GPR3
0851     EXCEPTION_LOAD_GPR2
0852 
0853     l.rfe                              // SR <- ESR, PC <- EPC
0854 
0855 exit_with_no_dtranslation:
0856     /* EA out of memory or not in supervisor mode */
0857     EXCEPTION_LOAD_GPR6
0858     EXCEPTION_LOAD_GPR4
0859     l.j _dispatch_bus_fault
0860 
0861 /* ---[ boot itlb miss handler ]----------------------------------------- */
0862 
0863 boot_itlb_miss_handler:
0864 
0865 /* mask for ITLB_MR register: - sets V (valid) bit,
0866  *                            - sets bits belonging to VPN (15-12)
0867  */
0868 #define ITLB_MR_MASK 0xfffff001
0869 
0870 /* mask for ITLB_TR register: - sets A (access) bit,
0871  *                            - sets SXE (superuser execute) bit
0872  *                            - sets bits belonging to VPN (15-12)
0873  */
0874 #define ITLB_TR_MASK 0xfffff050
0875 
0876 /*
0877 #define VPN_MASK 0xffffe000
0878 #define PPN_MASK 0xffffe000
0879 */
0880 
0881 
0882 
0883     EXCEPTION_STORE_GPR2
0884     EXCEPTION_STORE_GPR3
0885     EXCEPTION_STORE_GPR4
0886     EXCEPTION_STORE_GPR5
0887     EXCEPTION_STORE_GPR6
0888 
0889 #if 0
0890     l.mfspr r6,r0,SPR_ESR_BASE         //
0891     l.andi  r6,r6,SPR_SR_SM            // are we in kernel mode ?
0892     l.sfeqi r6,0                       // r6 == 0x1 --> SM
0893     l.bf    exit_with_no_itranslation
0894     l.nop
0895 #endif
0896 
0897 
0898     l.mfspr r4,r0,SPR_EEAR_BASE        // get the offending EA
0899 
0900 earlyearly:
0901     CLEAR_GPR(r6)
0902 
0903     l.srli  r3,r4,0xd                  // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
0904 
0905     l.mfspr r6, r0, SPR_IMMUCFGR
0906     l.andi  r6, r6, SPR_IMMUCFGR_NTS
0907     l.srli  r6, r6, SPR_IMMUCFGR_NTS_OFF
0908     l.ori   r5, r0, 0x1
0909     l.sll   r5, r5, r6  // r5 = number IMMU sets from IMMUCFGR
0910     l.addi  r6, r5, -1      // r6 = nsets mask
0911     l.and   r2, r3, r6  // r2 <- r3 % NSETS_MASK
0912 
0913     l.or    r6,r6,r4                   // r6 <- r4
0914     l.ori   r6,r6,~(VPN_MASK)          // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
0915     l.movhi r5,hi(ITLB_MR_MASK)        // r5 <- ffff:0000.x000
0916     l.ori   r5,r5,lo(ITLB_MR_MASK)     // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
0917     l.and   r5,r5,r6                   // r5 <- VPN :VPN .x001 - we have ITLBMR entry
0918     l.mtspr r2,r5,SPR_ITLBMR_BASE(0)   // set ITLBMR
0919 
0920     /*
0921      * set up ITLB with no translation for EA <= 0x0fffffff
0922      *
0923      * we need this for head.S mapping (EA = PA). if we move all functions
0924      * which run with mmu enabled into entry.S, we might be able to eliminate this.
0925      *
0926      */
0927     LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
0928     l.sfgeu  r6,r4                     // flag if r6 >= r4 (if 0xb0ffffff >= EA)
0929     l.bf     1f                        // goto out
0930     l.and    r3,r4,r4                  // delay slot :: 24 <- r4 (if flag==1)
0931 
0932     tophys(r3,r4)                      // r3 <- PA
0933 1:
0934     l.ori   r3,r3,~(PPN_MASK)          // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
0935     l.movhi r5,hi(ITLB_TR_MASK)        // r5 <- ffff:0000.x000
0936     l.ori   r5,r5,lo(ITLB_TR_MASK)     // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
0937     l.and   r5,r5,r3                   // r5 <- PPN :PPN .x050 - we have ITLBTR entry
0938     l.mtspr r2,r5,SPR_ITLBTR_BASE(0)   // set ITLBTR
0939 
0940     EXCEPTION_LOAD_GPR6
0941     EXCEPTION_LOAD_GPR5
0942     EXCEPTION_LOAD_GPR4
0943     EXCEPTION_LOAD_GPR3
0944     EXCEPTION_LOAD_GPR2
0945 
0946     l.rfe                              // SR <- ESR, PC <- EPC
0947 
0948 exit_with_no_itranslation:
0949     EXCEPTION_LOAD_GPR4
0950     EXCEPTION_LOAD_GPR6
0951     l.j    _dispatch_bus_fault
0952     l.nop
0953 
0954 /* ====================================================================== */
0955 /*
0956  * Stuff below here shouldn't go into .head section... maybe this stuff
0957  * can be moved to entry.S ???
0958  */
0959 
0960 /* ==============================================[ DTLB miss handler ]=== */
0961 
0962 /*
0963  * Comments:
0964  *   Exception handlers are entered with MMU off so the following handler
0965  *   needs to use physical addressing
0966  *
0967  */
0968 
0969     .text
0970 ENTRY(dtlb_miss_handler)
0971     EXCEPTION_STORE_GPR2
0972     EXCEPTION_STORE_GPR3
0973     EXCEPTION_STORE_GPR4
0974     EXCEPTION_STORE_GPR5
0975     EXCEPTION_STORE_GPR6
0976     /*
0977      * get EA of the miss
0978      */
0979     l.mfspr r2,r0,SPR_EEAR_BASE
0980     /*
0981      * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
0982      */
0983     GET_CURRENT_PGD(r3,r5)      // r3 is current_pgd, r5 is temp
0984     l.srli  r4,r2,0x18      // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
0985     l.slli  r4,r4,0x2       // to get address << 2
0986     l.add   r5,r4,r3        // r4 is pgd_index(daddr)
0987     /*
0988      * if (pmd_none(*pmd))
0989      *   goto pmd_none:
0990      */
0991     tophys  (r4,r5)
0992     l.lwz   r3,0x0(r4)      // get *pmd value
0993     l.sfne  r3,r0
0994     l.bnf   d_pmd_none
0995      l.andi r3,r3,~PAGE_MASK //0x1fff       // ~PAGE_MASK
0996     /*
0997      * if (pmd_bad(*pmd))
0998      *   pmd_clear(pmd)
0999      *   goto pmd_bad:
1000      */
1001 //  l.sfeq  r3,r0           // check *pmd value
1002 //  l.bf    d_pmd_good
1003     l.addi  r3,r0,0xffffe000    // PAGE_MASK
1004 //  l.j d_pmd_bad
1005 //  l.sw    0x0(r4),r0      // clear pmd
1006 d_pmd_good:
1007     /*
1008      * pte = *pte_offset(pmd, daddr);
1009      */
1010     l.lwz   r4,0x0(r4)      // get **pmd value
1011     l.and   r4,r4,r3        // & PAGE_MASK
1012     l.srli  r5,r2,0xd       // >> PAGE_SHIFT, r2 == EEAR
1013     l.andi  r3,r5,0x7ff     // (1UL << PAGE_SHIFT - 2) - 1
1014     l.slli  r3,r3,0x2       // to get address << 2
1015     l.add   r3,r3,r4
1016     l.lwz   r2,0x0(r3)      // this is pte at last
1017     /*
1018      * if (!pte_present(pte))
1019      */
1020     l.andi  r4,r2,0x1
1021     l.sfne  r4,r0           // is pte present
1022     l.bnf   d_pte_not_present
1023     l.addi  r3,r0,0xffffe3fa    // PAGE_MASK | DTLB_UP_CONVERT_MASK
1024     /*
1025      * fill DTLB TR register
1026      */
1027     l.and   r4,r2,r3        // apply the mask
1028     // Determine number of DMMU sets
1029     l.mfspr r6, r0, SPR_DMMUCFGR
1030     l.andi  r6, r6, SPR_DMMUCFGR_NTS
1031     l.srli  r6, r6, SPR_DMMUCFGR_NTS_OFF
1032     l.ori   r3, r0, 0x1
1033     l.sll   r3, r3, r6  // r3 = number DMMU sets DMMUCFGR
1034     l.addi  r6, r3, -1      // r6 = nsets mask
1035     l.and   r5, r5, r6  // calc offset:  & (NUM_TLB_ENTRIES-1)
1036                                                        //NUM_TLB_ENTRIES
1037     l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1038     /*
1039      * fill DTLB MR register
1040      */
1041     l.mfspr r2,r0,SPR_EEAR_BASE
1042     l.addi  r3,r0,0xffffe000    // PAGE_MASK
1043     l.and   r4,r2,r3        // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1044     l.ori   r4,r4,0x1       // set hardware valid bit: DTBL_MR entry
1045     l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1046 
1047     EXCEPTION_LOAD_GPR2
1048     EXCEPTION_LOAD_GPR3
1049     EXCEPTION_LOAD_GPR4
1050     EXCEPTION_LOAD_GPR5
1051     EXCEPTION_LOAD_GPR6
1052     l.rfe
1053 d_pmd_bad:
1054     l.nop   1
1055     EXCEPTION_LOAD_GPR2
1056     EXCEPTION_LOAD_GPR3
1057     EXCEPTION_LOAD_GPR4
1058     EXCEPTION_LOAD_GPR5
1059     EXCEPTION_LOAD_GPR6
1060     l.rfe
1061 d_pmd_none:
1062 d_pte_not_present:
1063     EXCEPTION_LOAD_GPR2
1064     EXCEPTION_LOAD_GPR3
1065     EXCEPTION_LOAD_GPR4
1066     EXCEPTION_LOAD_GPR5
1067     EXCEPTION_LOAD_GPR6
1068     EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
1069 
1070 /* ==============================================[ ITLB miss handler ]=== */
1071 ENTRY(itlb_miss_handler)
1072     EXCEPTION_STORE_GPR2
1073     EXCEPTION_STORE_GPR3
1074     EXCEPTION_STORE_GPR4
1075     EXCEPTION_STORE_GPR5
1076     EXCEPTION_STORE_GPR6
1077     /*
1078      * get EA of the miss
1079      */
1080     l.mfspr r2,r0,SPR_EEAR_BASE
1081 
1082     /*
1083      * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1084      *
1085      */
1086     GET_CURRENT_PGD(r3,r5)      // r3 is current_pgd, r5 is temp
1087     l.srli  r4,r2,0x18      // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1088     l.slli  r4,r4,0x2       // to get address << 2
1089     l.add   r5,r4,r3        // r4 is pgd_index(daddr)
1090     /*
1091      * if (pmd_none(*pmd))
1092      *   goto pmd_none:
1093      */
1094     tophys  (r4,r5)
1095     l.lwz   r3,0x0(r4)      // get *pmd value
1096     l.sfne  r3,r0
1097     l.bnf   i_pmd_none
1098     l.andi  r3,r3,0x1fff        // ~PAGE_MASK
1099     /*
1100      * if (pmd_bad(*pmd))
1101      *   pmd_clear(pmd)
1102      *   goto pmd_bad:
1103      */
1104 
1105 //  l.sfeq  r3,r0           // check *pmd value
1106 //  l.bf    i_pmd_good
1107     l.addi  r3,r0,0xffffe000    // PAGE_MASK
1108 //  l.j i_pmd_bad
1109 //  l.sw    0x0(r4),r0      // clear pmd
1110 
1111 i_pmd_good:
1112     /*
1113      * pte = *pte_offset(pmd, iaddr);
1114      *
1115      */
1116     l.lwz   r4,0x0(r4)      // get **pmd value
1117     l.and   r4,r4,r3        // & PAGE_MASK
1118     l.srli  r5,r2,0xd       // >> PAGE_SHIFT, r2 == EEAR
1119     l.andi  r3,r5,0x7ff     // (1UL << PAGE_SHIFT - 2) - 1
1120     l.slli  r3,r3,0x2       // to get address << 2
1121     l.add   r3,r3,r4
1122     l.lwz   r2,0x0(r3)      // this is pte at last
1123     /*
1124      * if (!pte_present(pte))
1125      *
1126      */
1127     l.andi  r4,r2,0x1
1128     l.sfne  r4,r0           // is pte present
1129     l.bnf   i_pte_not_present
1130     l.addi  r3,r0,0xffffe03a    // PAGE_MASK | ITLB_UP_CONVERT_MASK
1131     /*
1132      * fill ITLB TR register
1133      */
1134     l.and   r4,r2,r3        // apply the mask
1135     l.andi  r3,r2,0x7c0     // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE |  _PAGE_URE | _PAGE_UWE
1136 //  l.andi  r3,r2,0x400     // _PAGE_EXEC
1137     l.sfeq  r3,r0
1138     l.bf    itlb_tr_fill //_workaround
1139     // Determine number of IMMU sets
1140     l.mfspr r6, r0, SPR_IMMUCFGR
1141     l.andi  r6, r6, SPR_IMMUCFGR_NTS
1142     l.srli  r6, r6, SPR_IMMUCFGR_NTS_OFF
1143     l.ori   r3, r0, 0x1
1144     l.sll   r3, r3, r6  // r3 = number IMMU sets IMMUCFGR
1145     l.addi  r6, r3, -1      // r6 = nsets mask
1146     l.and   r5, r5, r6  // calc offset:  & (NUM_TLB_ENTRIES-1)
1147 
1148 /*
1149  * __PHX__ :: fixme
1150  * we should not just blindly set executable flags,
1151  * but it does help with ping. the clean way would be to find out
1152  * (and fix it) why stack doesn't have execution permissions
1153  */
1154 
1155 itlb_tr_fill_workaround:
1156     l.ori   r4,r4,0xc0      // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1157 itlb_tr_fill:
1158     l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1159     /*
1160      * fill DTLB MR register
1161      */
1162     l.mfspr r2,r0,SPR_EEAR_BASE
1163     l.addi  r3,r0,0xffffe000    // PAGE_MASK
1164     l.and   r4,r2,r3        // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1165     l.ori   r4,r4,0x1       // set hardware valid bit: DTBL_MR entry
1166     l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1167 
1168     EXCEPTION_LOAD_GPR2
1169     EXCEPTION_LOAD_GPR3
1170     EXCEPTION_LOAD_GPR4
1171     EXCEPTION_LOAD_GPR5
1172     EXCEPTION_LOAD_GPR6
1173     l.rfe
1174 
1175 i_pmd_bad:
1176     l.nop   1
1177     EXCEPTION_LOAD_GPR2
1178     EXCEPTION_LOAD_GPR3
1179     EXCEPTION_LOAD_GPR4
1180     EXCEPTION_LOAD_GPR5
1181     EXCEPTION_LOAD_GPR6
1182     l.rfe
1183 i_pmd_none:
1184 i_pte_not_present:
1185     EXCEPTION_LOAD_GPR2
1186     EXCEPTION_LOAD_GPR3
1187     EXCEPTION_LOAD_GPR4
1188     EXCEPTION_LOAD_GPR5
1189     EXCEPTION_LOAD_GPR6
1190     EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
1191 
1192 /* ==============================================[ boot tlb handlers ]=== */
1193 
1194 
1195 /* =================================================[ debugging aids ]=== */
1196 
1197     .align 64
1198 _immu_trampoline:
1199     .space 64
1200 _immu_trampoline_top:
1201 
1202 #define TRAMP_SLOT_0        (0x0)
1203 #define TRAMP_SLOT_1        (0x4)
1204 #define TRAMP_SLOT_2        (0x8)
1205 #define TRAMP_SLOT_3        (0xc)
1206 #define TRAMP_SLOT_4        (0x10)
1207 #define TRAMP_SLOT_5        (0x14)
1208 #define TRAMP_FRAME_SIZE    (0x18)
1209 
1210 ENTRY(_immu_trampoline_workaround)
1211     // r2 EEA
1212     // r6 is physical EEA
1213     tophys(r6,r2)
1214 
1215     LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1216     tophys  (r3,r5)         // r3 is trampoline (physical)
1217 
1218     LOAD_SYMBOL_2_GPR(r4,0x15000000)
1219     l.sw    TRAMP_SLOT_0(r3),r4
1220     l.sw    TRAMP_SLOT_1(r3),r4
1221     l.sw    TRAMP_SLOT_4(r3),r4
1222     l.sw    TRAMP_SLOT_5(r3),r4
1223 
1224                     // EPC = EEA - 0x4
1225     l.lwz   r4,0x0(r6)      // load op @ EEA + 0x0 (fc address)
1226     l.sw    TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1227     l.lwz   r4,-0x4(r6)     // load op @ EEA - 0x4 (f8 address)
1228     l.sw    TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1229 
1230     l.srli  r5,r4,26                // check opcode for write access
1231     l.sfeqi r5,0                    // l.j
1232     l.bf    0f
1233     l.sfeqi r5,0x11                 // l.jr
1234     l.bf    1f
1235     l.sfeqi r5,1                    // l.jal
1236     l.bf    2f
1237     l.sfeqi r5,0x12                 // l.jalr
1238     l.bf    3f
1239     l.sfeqi r5,3                    // l.bnf
1240     l.bf    4f
1241     l.sfeqi r5,4                    // l.bf
1242     l.bf    5f
1243 99:
1244     l.nop
1245     l.j 99b         // should never happen
1246     l.nop   1
1247 
1248     // r2 is EEA
1249     // r3 is trampoline address (physical)
1250     // r4 is instruction
1251     // r6 is physical(EEA)
1252     //
1253     // r5
1254 
1255 2:  // l.jal
1256 
1257     /* 19 20 aa aa  l.movhi r9,0xaaaa
1258      * a9 29 bb bb  l.ori   r9,0xbbbb
1259      *
1260      * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1261      */
1262 
1263     l.addi  r6,r2,0x4       // this is 0xaaaabbbb
1264 
1265                     // l.movhi r9,0xaaaa
1266     l.ori   r5,r0,0x1920        // 0x1920 == l.movhi r9
1267     l.sh    (TRAMP_SLOT_0+0x0)(r3),r5
1268     l.srli  r5,r6,16
1269     l.sh    (TRAMP_SLOT_0+0x2)(r3),r5
1270 
1271                     // l.ori   r9,0xbbbb
1272     l.ori   r5,r0,0xa929        // 0xa929 == l.ori r9
1273     l.sh    (TRAMP_SLOT_1+0x0)(r3),r5
1274     l.andi  r5,r6,0xffff
1275     l.sh    (TRAMP_SLOT_1+0x2)(r3),r5
1276 
1277     /* falthrough, need to set up new jump offset */
1278 
1279 
1280 0:  // l.j
1281     l.slli  r6,r4,6         // original offset shifted left 6 - 2
1282 //  l.srli  r6,r6,6         // original offset shifted right 2
1283 
1284     l.slli  r4,r2,4         // old jump position: EEA shifted left 4
1285 //  l.srli  r4,r4,6         // old jump position: shifted right 2
1286 
1287     l.addi  r5,r3,0xc       // new jump position (physical)
1288     l.slli  r5,r5,4         // new jump position: shifted left 4
1289 
1290     // calculate new jump offset
1291     // new_off = old_off + (old_jump - new_jump)
1292 
1293     l.sub   r5,r4,r5        // old_jump - new_jump
1294     l.add   r5,r6,r5        // orig_off + (old_jump - new_jump)
1295     l.srli  r5,r5,6         // new offset shifted right 2
1296 
1297     // r5 is new jump offset
1298                     // l.j has opcode 0x0...
1299     l.sw    TRAMP_SLOT_2(r3),r5 // write it back
1300 
1301     l.j trampoline_out
1302     l.nop
1303 
1304 /* ----------------------------- */
1305 
1306 3:  // l.jalr
1307 
1308     /* 19 20 aa aa  l.movhi r9,0xaaaa
1309      * a9 29 bb bb  l.ori   r9,0xbbbb
1310      *
1311      * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1312      */
1313 
1314     l.addi  r6,r2,0x4       // this is 0xaaaabbbb
1315 
1316                     // l.movhi r9,0xaaaa
1317     l.ori   r5,r0,0x1920        // 0x1920 == l.movhi r9
1318     l.sh    (TRAMP_SLOT_0+0x0)(r3),r5
1319     l.srli  r5,r6,16
1320     l.sh    (TRAMP_SLOT_0+0x2)(r3),r5
1321 
1322                     // l.ori   r9,0xbbbb
1323     l.ori   r5,r0,0xa929        // 0xa929 == l.ori r9
1324     l.sh    (TRAMP_SLOT_1+0x0)(r3),r5
1325     l.andi  r5,r6,0xffff
1326     l.sh    (TRAMP_SLOT_1+0x2)(r3),r5
1327 
1328     l.lhz   r5,(TRAMP_SLOT_2+0x0)(r3)   // load hi part of jump instruction
1329     l.andi  r5,r5,0x3ff     // clear out opcode part
1330     l.ori   r5,r5,0x4400        // opcode changed from l.jalr -> l.jr
1331     l.sh    (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1332 
1333     /* falthrough */
1334 
1335 1:  // l.jr
1336     l.j trampoline_out
1337     l.nop
1338 
1339 /* ----------------------------- */
1340 
1341 4:  // l.bnf
1342 5:  // l.bf
1343     l.slli  r6,r4,6         // original offset shifted left 6 - 2
1344 //  l.srli  r6,r6,6         // original offset shifted right 2
1345 
1346     l.slli  r4,r2,4         // old jump position: EEA shifted left 4
1347 //  l.srli  r4,r4,6         // old jump position: shifted right 2
1348 
1349     l.addi  r5,r3,0xc       // new jump position (physical)
1350     l.slli  r5,r5,4         // new jump position: shifted left 4
1351 
1352     // calculate new jump offset
1353     // new_off = old_off + (old_jump - new_jump)
1354 
1355     l.add   r6,r6,r4        // (orig_off + old_jump)
1356     l.sub   r6,r6,r5        // (orig_off + old_jump) - new_jump
1357     l.srli  r6,r6,6         // new offset shifted right 2
1358 
1359     // r6 is new jump offset
1360     l.lwz   r4,(TRAMP_SLOT_2+0x0)(r3)   // load jump instruction
1361     l.srli  r4,r4,16
1362     l.andi  r4,r4,0xfc00        // get opcode part
1363     l.slli  r4,r4,16
1364     l.or    r6,r4,r6        // l.b(n)f new offset
1365     l.sw    TRAMP_SLOT_2(r3),r6 // write it back
1366 
1367     /* we need to add l.j to EEA + 0x8 */
1368     tophys  (r4,r2)         // may not be needed (due to shifts down_
1369     l.addi  r4,r4,(0x8 - 0x8)   // jump target = r2 + 0x8 (compensate for 0x8)
1370                     // jump position = r5 + 0x8 (0x8 compensated)
1371     l.sub   r4,r4,r5        // jump offset = target - new_position + 0x8
1372 
1373     l.slli  r4,r4,4         // the amount of info in imediate of jump
1374     l.srli  r4,r4,6         // jump instruction with offset
1375     l.sw    TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1376 
1377     /* fallthrough */
1378 
1379 trampoline_out:
1380     // set up new EPC to point to our trampoline code
1381     LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1382     l.mtspr r0,r5,SPR_EPCR_BASE
1383 
1384     // immu_trampoline is (4x) CACHE_LINE aligned
1385     // and only 6 instructions long,
1386     // so we need to invalidate only 2 lines
1387 
1388     /* Establish cache block size
1389        If BS=0, 16;
1390        If BS=1, 32;
1391        r14 contain block size
1392     */
1393     l.mfspr r21,r0,SPR_ICCFGR
1394     l.andi  r21,r21,SPR_ICCFGR_CBS
1395     l.srli  r21,r21,7
1396     l.ori   r23,r0,16
1397     l.sll   r14,r23,r21
1398 
1399     l.mtspr r0,r5,SPR_ICBIR
1400     l.add   r5,r5,r14
1401     l.mtspr r0,r5,SPR_ICBIR
1402 
1403     l.jr    r9
1404     l.nop
1405 
1406 
1407 /*
1408  * DSCR: prints a string referenced by r3.
1409  *
1410  * PRMS: r3         - address of the first character of null
1411  *          terminated string to be printed
1412  *
1413  * PREQ: UART at UART_BASE_ADD has to be initialized
1414  *
1415  * POST: caller should be aware that r3, r9 are changed
1416  */
1417 ENTRY(_emergency_print)
1418     EMERGENCY_PRINT_STORE_GPR4
1419     EMERGENCY_PRINT_STORE_GPR5
1420     EMERGENCY_PRINT_STORE_GPR6
1421     EMERGENCY_PRINT_STORE_GPR7
1422 2:
1423     l.lbz   r7,0(r3)
1424     l.sfeq  r7,r0
1425     l.bf    9f
1426     l.nop
1427 
1428 // putc:
1429     l.movhi r4,hi(UART_BASE_ADD)
1430 
1431     l.addi  r6,r0,0x20
1432 1:      l.lbz   r5,5(r4)
1433     l.andi  r5,r5,0x20
1434     l.sfeq  r5,r6
1435     l.bnf   1b
1436     l.nop
1437 
1438     l.sb    0(r4),r7
1439 
1440     l.addi  r6,r0,0x60
1441 1:      l.lbz   r5,5(r4)
1442     l.andi  r5,r5,0x60
1443     l.sfeq  r5,r6
1444     l.bnf   1b
1445     l.nop
1446 
1447     /* next character */
1448     l.j 2b
1449     l.addi  r3,r3,0x1
1450 
1451 9:
1452     EMERGENCY_PRINT_LOAD_GPR7
1453     EMERGENCY_PRINT_LOAD_GPR6
1454     EMERGENCY_PRINT_LOAD_GPR5
1455     EMERGENCY_PRINT_LOAD_GPR4
1456     l.jr    r9
1457     l.nop
1458 
1459 ENTRY(_emergency_print_nr)
1460     EMERGENCY_PRINT_STORE_GPR4
1461     EMERGENCY_PRINT_STORE_GPR5
1462     EMERGENCY_PRINT_STORE_GPR6
1463     EMERGENCY_PRINT_STORE_GPR7
1464     EMERGENCY_PRINT_STORE_GPR8
1465 
1466     l.addi  r8,r0,32        // shift register
1467 
1468 1:  /* remove leading zeros */
1469     l.addi  r8,r8,-0x4
1470     l.srl   r7,r3,r8
1471     l.andi  r7,r7,0xf
1472 
1473     /* don't skip the last zero if number == 0x0 */
1474     l.sfeqi r8,0x4
1475     l.bf    2f
1476     l.nop
1477 
1478     l.sfeq  r7,r0
1479     l.bf    1b
1480     l.nop
1481 
1482 2:
1483     l.srl   r7,r3,r8
1484 
1485     l.andi  r7,r7,0xf
1486     l.sflts r8,r0
1487     l.bf    9f
1488 
1489     l.sfgtui r7,0x9
1490     l.bnf   8f
1491     l.nop
1492     l.addi  r7,r7,0x27
1493 
1494 8:
1495     l.addi  r7,r7,0x30
1496 // putc:
1497     l.movhi r4,hi(UART_BASE_ADD)
1498 
1499     l.addi  r6,r0,0x20
1500 1:      l.lbz   r5,5(r4)
1501     l.andi  r5,r5,0x20
1502     l.sfeq  r5,r6
1503     l.bnf   1b
1504     l.nop
1505 
1506     l.sb    0(r4),r7
1507 
1508     l.addi  r6,r0,0x60
1509 1:      l.lbz   r5,5(r4)
1510     l.andi  r5,r5,0x60
1511     l.sfeq  r5,r6
1512     l.bnf   1b
1513     l.nop
1514 
1515     /* next character */
1516     l.j 2b
1517     l.addi  r8,r8,-0x4
1518 
1519 9:
1520     EMERGENCY_PRINT_LOAD_GPR8
1521     EMERGENCY_PRINT_LOAD_GPR7
1522     EMERGENCY_PRINT_LOAD_GPR6
1523     EMERGENCY_PRINT_LOAD_GPR5
1524     EMERGENCY_PRINT_LOAD_GPR4
1525     l.jr    r9
1526     l.nop
1527 
1528 
1529 /*
1530  * This should be used for debugging only.
1531  * It messes up the Linux early serial output
1532  * somehow, so use it sparingly and essentially
1533  * only if you need to debug something that goes wrong
1534  * before Linux gets the early serial going.
1535  *
1536  * Furthermore, you'll have to make sure you set the
1537  * UART_DEVISOR correctly according to the system
1538  * clock rate.
1539  *
1540  *
1541  */
1542 
1543 
1544 
1545 #define SYS_CLK            20000000
1546 //#define SYS_CLK            1843200
1547 #define OR32_CONSOLE_BAUD  115200
1548 #define UART_DIVISOR       SYS_CLK/(16*OR32_CONSOLE_BAUD)
1549 
1550 ENTRY(_early_uart_init)
1551     l.movhi r3,hi(UART_BASE_ADD)
1552 
1553     l.addi  r4,r0,0x7
1554     l.sb    0x2(r3),r4
1555 
1556     l.addi  r4,r0,0x0
1557     l.sb    0x1(r3),r4
1558 
1559     l.addi  r4,r0,0x3
1560     l.sb    0x3(r3),r4
1561 
1562     l.lbz   r5,3(r3)
1563     l.ori   r4,r5,0x80
1564     l.sb    0x3(r3),r4
1565     l.addi  r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1566     l.sb    UART_DLM(r3),r4
1567     l.addi  r4,r0,((UART_DIVISOR) & 0x000000ff)
1568     l.sb    UART_DLL(r3),r4
1569     l.sb    0x3(r3),r5
1570 
1571     l.jr    r9
1572     l.nop
1573 
1574 _string_copying_linux:
1575     .string "\n\n\n\n\n\rCopying Linux... \0"
1576 
1577 _string_ok_booting:
1578     .string "Ok, booting the kernel.\n\r\0"
1579 
1580 _string_unhandled_exception:
1581     .string "\n\rRunarunaround: Unhandled exception 0x\0"
1582 
1583 _string_epc_prefix:
1584     .string ": EPC=0x\0"
1585 
1586 _string_nl:
1587     .string "\n\r\0"
1588 
1589     .global _string_esr_irq_bug
1590 _string_esr_irq_bug:
1591     .string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
1592 
1593 
1594 
1595 /* ========================================[ page aligned structures ]=== */
1596 
1597 /*
1598  * .data section should be page aligned
1599  *  (look into arch/or32/kernel/vmlinux.lds)
1600  */
1601     .section .data,"aw"
1602     .align  8192
1603     .global  empty_zero_page
1604 empty_zero_page:
1605     .space  8192
1606 
1607     .global  swapper_pg_dir
1608 swapper_pg_dir:
1609     .space  8192
1610 
1611     .global _unhandled_stack
1612 _unhandled_stack:
1613     .space  8192
1614 _unhandled_stack_top:
1615 
1616 /* ============================================================[ EOF ]=== */