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0001 /*
0002  * File:    mca_asm.S
0003  * Purpose: assembly portion of the IA64 MCA handling
0004  *
0005  * Mods by cfleck to integrate into kernel build
0006  *
0007  * 2000-03-15 David Mosberger-Tang <davidm@hpl.hp.com>
0008  *      Added various stop bits to get a clean compile
0009  *
0010  * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
0011  *      Added code to save INIT handoff state in pt_regs format,
0012  *      switch to temp kstack, switch modes, jump to C INIT handler
0013  *
0014  * 2002-01-04 J.Hall <jenna.s.hall@intel.com>
0015  *      Before entering virtual mode code:
0016  *       1. Check for TLB CPU error
0017  *       2. Restore current thread pointer to kr6
0018  *       3. Move stack ptr 16 bytes to conform to C calling convention
0019  *
0020  * 2004-11-12 Russ Anderson <rja@sgi.com>
0021  *      Added per cpu MCA/INIT stack save areas.
0022  *
0023  * 2005-12-08 Keith Owens <kaos@sgi.com>
0024  *      Use per cpu MCA/INIT stacks for all data.
0025  */
0026 #include <linux/threads.h>
0027 
0028 #include <asm/asmmacro.h>
0029 #include <asm/pgtable.h>
0030 #include <asm/processor.h>
0031 #include <asm/mca_asm.h>
0032 #include <asm/mca.h>
0033 
0034 #include "entry.h"
0035 
0036 #define GET_IA64_MCA_DATA(reg)                      \
0037     GET_THIS_PADDR(reg, ia64_mca_data)              \
0038     ;;                              \
0039     ld8 reg=[reg]
0040 
0041     .global ia64_do_tlb_purge
0042     .global ia64_os_mca_dispatch
0043     .global ia64_os_init_on_kdump
0044     .global ia64_os_init_dispatch_monarch
0045     .global ia64_os_init_dispatch_slave
0046 
0047     .text
0048     .align 16
0049 
0050 //StartMain////////////////////////////////////////////////////////////////////
0051 
0052 /*
0053  * Just the TLB purge part is moved to a separate function
0054  * so we can re-use the code for cpu hotplug code as well
0055  * Caller should now setup b1, so we can branch once the
0056  * tlb flush is complete.
0057  */
0058 
0059 ia64_do_tlb_purge:
0060 #define O(member)   IA64_CPUINFO_##member##_OFFSET
0061 
0062     GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2
0063     ;;
0064     addl r17=O(PTCE_STRIDE),r2
0065     addl r2=O(PTCE_BASE),r2
0066     ;;
0067     ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
0068     ld4 r19=[r2],4                  // r19=ptce_count[0]
0069     ld4 r21=[r17],4                 // r21=ptce_stride[0]
0070     ;;
0071     ld4 r20=[r2]                    // r20=ptce_count[1]
0072     ld4 r22=[r17]                   // r22=ptce_stride[1]
0073     mov r24=0
0074     ;;
0075     adds r20=-1,r20
0076     ;;
0077 #undef O
0078 
0079 2:
0080     cmp.ltu p6,p7=r24,r19
0081 (p7)    br.cond.dpnt.few 4f
0082     mov ar.lc=r20
0083 3:
0084     ptc.e r18
0085     ;;
0086     add r18=r22,r18
0087     br.cloop.sptk.few 3b
0088     ;;
0089     add r18=r21,r18
0090     add r24=1,r24
0091     ;;
0092     br.sptk.few 2b
0093 4:
0094     srlz.i          // srlz.i implies srlz.d
0095     ;;
0096 
0097         // Now purge addresses formerly mapped by TR registers
0098     // 1. Purge ITR&DTR for kernel.
0099     movl r16=KERNEL_START
0100     mov r18=KERNEL_TR_PAGE_SHIFT<<2
0101     ;;
0102     ptr.i r16, r18
0103     ptr.d r16, r18
0104     ;;
0105     srlz.i
0106     ;;
0107     srlz.d
0108     ;;
0109     // 3. Purge ITR for PAL code.
0110     GET_THIS_PADDR(r2, ia64_mca_pal_base)
0111     ;;
0112     ld8 r16=[r2]
0113     mov r18=IA64_GRANULE_SHIFT<<2
0114     ;;
0115     ptr.i r16,r18
0116     ;;
0117     srlz.i
0118     ;;
0119     // 4. Purge DTR for stack.
0120     mov r16=IA64_KR(CURRENT_STACK)
0121     ;;
0122     shl r16=r16,IA64_GRANULE_SHIFT
0123     movl r19=PAGE_OFFSET
0124     ;;
0125     add r16=r19,r16
0126     mov r18=IA64_GRANULE_SHIFT<<2
0127     ;;
0128     ptr.d r16,r18
0129     ;;
0130     srlz.i
0131     ;;
0132     // Now branch away to caller.
0133     br.sptk.many b1
0134     ;;
0135 
0136 //EndMain//////////////////////////////////////////////////////////////////////
0137 
0138 //StartMain////////////////////////////////////////////////////////////////////
0139 
0140 ia64_os_mca_dispatch:
0141     mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
0142     LOAD_PHYSICAL(p0,r2,1f)         // return address
0143     mov r19=1               // All MCA events are treated as monarch (for now)
0144     br.sptk ia64_state_save         // save the state that is not in minstate
0145 1:
0146 
0147     GET_IA64_MCA_DATA(r2)
0148     // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
0149     ;;
0150     add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+SOS(PROC_STATE_PARAM), r2
0151     ;;
0152     ld8 r18=[r3]                // Get processor state parameter on existing PALE_CHECK.
0153     ;;
0154     tbit.nz p6,p7=r18,60
0155 (p7)    br.spnt done_tlb_purge_and_reload
0156 
0157     // The following code purges TC and TR entries. Then reload all TC entries.
0158     // Purge percpu data TC entries.
0159 begin_tlb_purge_and_reload:
0160     movl r18=ia64_reload_tr;;
0161     LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
0162     mov b1=r18;;
0163     br.sptk.many ia64_do_tlb_purge;;
0164 
0165 ia64_reload_tr:
0166     // Finally reload the TR registers.
0167     // 1. Reload DTR/ITR registers for kernel.
0168     mov r18=KERNEL_TR_PAGE_SHIFT<<2
0169     movl r17=KERNEL_START
0170     ;;
0171     mov cr.itir=r18
0172     mov cr.ifa=r17
0173         mov r16=IA64_TR_KERNEL
0174     mov r19=ip
0175     movl r18=PAGE_KERNEL
0176     ;;
0177         dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
0178     ;;
0179     or r18=r17,r18
0180     ;;
0181         itr.i itr[r16]=r18
0182     ;;
0183         itr.d dtr[r16]=r18
0184         ;;
0185     srlz.i
0186     srlz.d
0187     ;;
0188     // 3. Reload ITR for PAL code.
0189     GET_THIS_PADDR(r2, ia64_mca_pal_pte)
0190     ;;
0191     ld8 r18=[r2]            // load PAL PTE
0192     ;;
0193     GET_THIS_PADDR(r2, ia64_mca_pal_base)
0194     ;;
0195     ld8 r16=[r2]            // load PAL vaddr
0196     mov r19=IA64_GRANULE_SHIFT<<2
0197     ;;
0198     mov cr.itir=r19
0199     mov cr.ifa=r16
0200     mov r20=IA64_TR_PALCODE
0201     ;;
0202     itr.i itr[r20]=r18
0203     ;;
0204     srlz.i
0205     ;;
0206     // 4. Reload DTR for stack.
0207     mov r16=IA64_KR(CURRENT_STACK)
0208     ;;
0209     shl r16=r16,IA64_GRANULE_SHIFT
0210     movl r19=PAGE_OFFSET
0211     ;;
0212     add r18=r19,r16
0213     movl r20=PAGE_KERNEL
0214     ;;
0215     add r16=r20,r16
0216     mov r19=IA64_GRANULE_SHIFT<<2
0217     ;;
0218     mov cr.itir=r19
0219     mov cr.ifa=r18
0220     mov r20=IA64_TR_CURRENT_STACK
0221     ;;
0222     itr.d dtr[r20]=r16
0223     GET_THIS_PADDR(r2, ia64_mca_tr_reload)
0224     mov r18 = 1
0225     ;;
0226     srlz.d
0227     ;;
0228     st8 [r2] =r18
0229     ;;
0230 
0231 done_tlb_purge_and_reload:
0232 
0233     // switch to per cpu MCA stack
0234     mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
0235     LOAD_PHYSICAL(p0,r2,1f)         // return address
0236     br.sptk ia64_new_stack
0237 1:
0238 
0239     // everything saved, now we can set the kernel registers
0240     mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
0241     LOAD_PHYSICAL(p0,r2,1f)         // return address
0242     br.sptk ia64_set_kernel_registers
0243 1:
0244 
0245     // This must be done in physical mode
0246     GET_IA64_MCA_DATA(r2)
0247     ;;
0248     mov r7=r2
0249 
0250         // Enter virtual mode from physical mode
0251     VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
0252 
0253     // This code returns to SAL via SOS r2, in general SAL has no unwind
0254     // data.  To get a clean termination when backtracing the C MCA/INIT
0255     // handler, set a dummy return address of 0 in this routine.  That
0256     // requires that ia64_os_mca_virtual_begin be a global function.
0257 ENTRY(ia64_os_mca_virtual_begin)
0258     .prologue
0259     .save rp,r0
0260     .body
0261 
0262     mov ar.rsc=3                // set eager mode for C handler
0263     mov r2=r7               // see GET_IA64_MCA_DATA above
0264     ;;
0265 
0266     // Call virtual mode handler
0267     alloc r14=ar.pfs,0,0,3,0
0268     ;;
0269     DATA_PA_TO_VA(r2,r7)
0270     ;;
0271     add out0=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
0272     add out1=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
0273     add out2=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET, r2
0274     br.call.sptk.many    b0=ia64_mca_handler
0275 
0276     // Revert back to physical mode before going back to SAL
0277     PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
0278 ia64_os_mca_virtual_end:
0279 
0280 END(ia64_os_mca_virtual_begin)
0281 
0282     // switch back to previous stack
0283     alloc r14=ar.pfs,0,0,0,0        // remove the MCA handler frame
0284     mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
0285     LOAD_PHYSICAL(p0,r2,1f)         // return address
0286     br.sptk ia64_old_stack
0287 1:
0288 
0289     mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
0290     LOAD_PHYSICAL(p0,r2,1f)         // return address
0291     br.sptk ia64_state_restore      // restore the SAL state
0292 1:
0293 
0294     mov     b0=r12          // SAL_CHECK return address
0295 
0296     br      b0
0297 
0298 //EndMain//////////////////////////////////////////////////////////////////////
0299 
0300 //StartMain////////////////////////////////////////////////////////////////////
0301 
0302 //
0303 // NOP init handler for kdump.  In panic situation, we may receive INIT
0304 // while kernel transition.  Since we initialize registers on leave from
0305 // current kernel, no longer monarch/slave handlers of current kernel in
0306 // virtual mode are called safely.
0307 // We can unregister these init handlers from SAL, however then the INIT
0308 // will result in warmboot by SAL and we cannot retrieve the crashdump.
0309 // Therefore register this NOP function to SAL, to prevent entering virtual
0310 // mode and resulting warmboot by SAL.
0311 //
0312 ia64_os_init_on_kdump:
0313     mov     r8=r0       // IA64_INIT_RESUME
0314     mov             r9=r10      // SAL_GP
0315     mov     r22=r17     // *minstate
0316     ;;
0317     mov     r10=r0      // return to same context
0318     mov     b0=r12      // SAL_CHECK return address
0319     br      b0
0320 
0321 //
0322 // SAL to OS entry point for INIT on all processors.  This has been defined for
0323 // registration purposes with SAL as a part of ia64_mca_init.  Monarch and
0324 // slave INIT have identical processing, except for the value of the
0325 // sos->monarch flag in r19.
0326 //
0327 
0328 ia64_os_init_dispatch_monarch:
0329     mov r19=1               // Bow, bow, ye lower middle classes!
0330     br.sptk ia64_os_init_dispatch
0331 
0332 ia64_os_init_dispatch_slave:
0333     mov r19=0               // <igor>yeth, mathter</igor>
0334 
0335 ia64_os_init_dispatch:
0336 
0337     mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET   // use the INIT stack
0338     LOAD_PHYSICAL(p0,r2,1f)         // return address
0339     br.sptk ia64_state_save         // save the state that is not in minstate
0340 1:
0341 
0342     // switch to per cpu INIT stack
0343     mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET   // use the INIT stack
0344     LOAD_PHYSICAL(p0,r2,1f)         // return address
0345     br.sptk ia64_new_stack
0346 1:
0347 
0348     // everything saved, now we can set the kernel registers
0349     mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET   // use the INIT stack
0350     LOAD_PHYSICAL(p0,r2,1f)         // return address
0351     br.sptk ia64_set_kernel_registers
0352 1:
0353 
0354     // This must be done in physical mode
0355     GET_IA64_MCA_DATA(r2)
0356     ;;
0357     mov r7=r2
0358 
0359         // Enter virtual mode from physical mode
0360     VIRTUAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_begin, r4)
0361 
0362     // This code returns to SAL via SOS r2, in general SAL has no unwind
0363     // data.  To get a clean termination when backtracing the C MCA/INIT
0364     // handler, set a dummy return address of 0 in this routine.  That
0365     // requires that ia64_os_init_virtual_begin be a global function.
0366 ENTRY(ia64_os_init_virtual_begin)
0367     .prologue
0368     .save rp,r0
0369     .body
0370 
0371     mov ar.rsc=3                // set eager mode for C handler
0372     mov r2=r7               // see GET_IA64_MCA_DATA above
0373     ;;
0374 
0375     // Call virtual mode handler
0376     alloc r14=ar.pfs,0,0,3,0
0377     ;;
0378     DATA_PA_TO_VA(r2,r7)
0379     ;;
0380     add out0=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
0381     add out1=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
0382     add out2=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SOS_OFFSET, r2
0383     br.call.sptk.many    b0=ia64_init_handler
0384 
0385     // Revert back to physical mode before going back to SAL
0386     PHYSICAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_end, r4)
0387 ia64_os_init_virtual_end:
0388 
0389 END(ia64_os_init_virtual_begin)
0390 
0391     mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET   // use the INIT stack
0392     LOAD_PHYSICAL(p0,r2,1f)         // return address
0393     br.sptk ia64_state_restore      // restore the SAL state
0394 1:
0395 
0396     // switch back to previous stack
0397     alloc r14=ar.pfs,0,0,0,0        // remove the INIT handler frame
0398     mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET   // use the INIT stack
0399     LOAD_PHYSICAL(p0,r2,1f)         // return address
0400     br.sptk ia64_old_stack
0401 1:
0402 
0403     mov     b0=r12          // SAL_CHECK return address
0404     br      b0
0405 
0406 //EndMain//////////////////////////////////////////////////////////////////////
0407 
0408 // common defines for the stubs
0409 #define ms      r4
0410 #define regs        r5
0411 #define temp1       r2  /* careful, it overlaps with input registers */
0412 #define temp2       r3  /* careful, it overlaps with input registers */
0413 #define temp3       r7
0414 #define temp4       r14
0415 
0416 
0417 //++
0418 // Name:
0419 //  ia64_state_save()
0420 //
0421 // Stub Description:
0422 //
0423 //  Save the state that is not in minstate.  This is sensitive to the layout of
0424 //  struct ia64_sal_os_state in mca.h.
0425 //
0426 //  r2 contains the return address, r3 contains either
0427 //  IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
0428 //
0429 //  The OS to SAL section of struct ia64_sal_os_state is set to a default
0430 //  value of cold boot (MCA) or warm boot (INIT) and return to the same
0431 //  context.  ia64_sal_os_state is also used to hold some registers that
0432 //  need to be saved and restored across the stack switches.
0433 //
0434 //  Most input registers to this stub come from PAL/SAL
0435 //  r1  os gp, physical
0436 //  r8  pal_proc entry point
0437 //  r9  sal_proc entry point
0438 //  r10 sal gp
0439 //  r11 MCA - rendevzous state, INIT - reason code
0440 //  r12 sal return address
0441 //  r17 pal min_state
0442 //  r18 processor state parameter
0443 //  r19 monarch flag, set by the caller of this routine
0444 //
0445 //  In addition to the SAL to OS state, this routine saves all the
0446 //  registers that appear in struct pt_regs and struct switch_stack,
0447 //  excluding those that are already in the PAL minstate area.  This
0448 //  results in a partial pt_regs and switch_stack, the C code copies the
0449 //  remaining registers from PAL minstate to pt_regs and switch_stack.  The
0450 //  resulting structures contain all the state of the original process when
0451 //  MCA/INIT occurred.
0452 //
0453 //--
0454 
0455 ia64_state_save:
0456     add regs=MCA_SOS_OFFSET, r3
0457     add ms=MCA_SOS_OFFSET+8, r3
0458     mov b0=r2       // save return address
0459     cmp.eq p1,p2=IA64_MCA_CPU_MCA_STACK_OFFSET, r3
0460     ;;
0461     GET_IA64_MCA_DATA(temp2)
0462     ;;
0463     add temp1=temp2, regs   // struct ia64_sal_os_state on MCA or INIT stack
0464     add temp2=temp2, ms // struct ia64_sal_os_state+8 on MCA or INIT stack
0465     ;;
0466     mov regs=temp1      // save the start of sos
0467     st8 [temp1]=r1,16   // os_gp
0468     st8 [temp2]=r8,16   // pal_proc
0469     ;;
0470     st8 [temp1]=r9,16   // sal_proc
0471     st8 [temp2]=r11,16  // rv_rc
0472     mov r11=cr.iipa
0473     ;;
0474     st8 [temp1]=r18     // proc_state_param
0475     st8 [temp2]=r19     // monarch
0476     mov r6=IA64_KR(CURRENT)
0477     add temp1=SOS(SAL_RA), regs
0478     add temp2=SOS(SAL_GP), regs
0479     ;;
0480     st8 [temp1]=r12,16  // sal_ra
0481     st8 [temp2]=r10,16  // sal_gp
0482     mov r12=cr.isr
0483     ;;
0484     st8 [temp1]=r17,16  // pal_min_state
0485     st8 [temp2]=r6,16   // prev_IA64_KR_CURRENT
0486     mov r6=IA64_KR(CURRENT_STACK)
0487     ;;
0488     st8 [temp1]=r6,16   // prev_IA64_KR_CURRENT_STACK
0489     st8 [temp2]=r0,16   // prev_task, starts off as NULL
0490     mov r6=cr.ifa
0491     ;;
0492     st8 [temp1]=r12,16  // cr.isr
0493     st8 [temp2]=r6,16   // cr.ifa
0494     mov r12=cr.itir
0495     ;;
0496     st8 [temp1]=r12,16  // cr.itir
0497     st8 [temp2]=r11,16  // cr.iipa
0498     mov r12=cr.iim
0499     ;;
0500     st8 [temp1]=r12     // cr.iim
0501 (p1)    mov r12=IA64_MCA_COLD_BOOT
0502 (p2)    mov r12=IA64_INIT_WARM_BOOT
0503     mov r6=cr.iha
0504     add temp1=SOS(OS_STATUS), regs
0505     ;;
0506     st8 [temp2]=r6      // cr.iha
0507     add temp2=SOS(CONTEXT), regs
0508     st8 [temp1]=r12     // os_status, default is cold boot
0509     mov r6=IA64_MCA_SAME_CONTEXT
0510     ;;
0511     st8 [temp2]=r6      // context, default is same context
0512 
0513     // Save the pt_regs data that is not in minstate.  The previous code
0514     // left regs at sos.
0515     add regs=MCA_PT_REGS_OFFSET-MCA_SOS_OFFSET, regs
0516     ;;
0517     add temp1=PT(B6), regs
0518     mov temp3=b6
0519     mov temp4=b7
0520     add temp2=PT(B7), regs
0521     ;;
0522     st8 [temp1]=temp3,PT(AR_CSD)-PT(B6)     // save b6
0523     st8 [temp2]=temp4,PT(AR_SSD)-PT(B7)     // save b7
0524     mov temp3=ar.csd
0525     mov temp4=ar.ssd
0526     cover                       // must be last in group
0527     ;;
0528     st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD)    // save ar.csd
0529     st8 [temp2]=temp4,PT(AR_PFS)-PT(AR_SSD)     // save ar.ssd
0530     mov temp3=ar.unat
0531     mov temp4=ar.pfs
0532     ;;
0533     st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT)   // save ar.unat
0534     st8 [temp2]=temp4,PT(AR_BSPSTORE)-PT(AR_PFS)    // save ar.pfs
0535     mov temp3=ar.rnat
0536     mov temp4=ar.bspstore
0537     ;;
0538     st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT)    // save ar.rnat
0539     st8 [temp2]=temp4,PT(AR_FPSR)-PT(AR_BSPSTORE)   // save ar.bspstore
0540     mov temp3=ar.bsp
0541     ;;
0542     sub temp3=temp3, temp4  // ar.bsp - ar.bspstore
0543     mov temp4=ar.fpsr
0544     ;;
0545     shl temp3=temp3,16  // compute ar.rsc to be used for "loadrs"
0546     ;;
0547     st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS)     // save loadrs
0548     st8 [temp2]=temp4,PT(F6)-PT(AR_FPSR)        // save ar.fpsr
0549     mov temp3=ar.ccv
0550     ;;
0551     st8 [temp1]=temp3,PT(F7)-PT(AR_CCV)     // save ar.ccv
0552     stf.spill [temp2]=f6,PT(F8)-PT(F6)
0553     ;;
0554     stf.spill [temp1]=f7,PT(F9)-PT(F7)
0555     stf.spill [temp2]=f8,PT(F10)-PT(F8)
0556     ;;
0557     stf.spill [temp1]=f9,PT(F11)-PT(F9)
0558     stf.spill [temp2]=f10
0559     ;;
0560     stf.spill [temp1]=f11
0561 
0562     // Save the switch_stack data that is not in minstate nor pt_regs.  The
0563     // previous code left regs at pt_regs.
0564     add regs=MCA_SWITCH_STACK_OFFSET-MCA_PT_REGS_OFFSET, regs
0565     ;;
0566     add temp1=SW(F2), regs
0567     add temp2=SW(F3), regs
0568     ;;
0569     stf.spill [temp1]=f2,32
0570     stf.spill [temp2]=f3,32
0571     ;;
0572     stf.spill [temp1]=f4,32
0573     stf.spill [temp2]=f5,32
0574     ;;
0575     stf.spill [temp1]=f12,32
0576     stf.spill [temp2]=f13,32
0577     ;;
0578     stf.spill [temp1]=f14,32
0579     stf.spill [temp2]=f15,32
0580     ;;
0581     stf.spill [temp1]=f16,32
0582     stf.spill [temp2]=f17,32
0583     ;;
0584     stf.spill [temp1]=f18,32
0585     stf.spill [temp2]=f19,32
0586     ;;
0587     stf.spill [temp1]=f20,32
0588     stf.spill [temp2]=f21,32
0589     ;;
0590     stf.spill [temp1]=f22,32
0591     stf.spill [temp2]=f23,32
0592     ;;
0593     stf.spill [temp1]=f24,32
0594     stf.spill [temp2]=f25,32
0595     ;;
0596     stf.spill [temp1]=f26,32
0597     stf.spill [temp2]=f27,32
0598     ;;
0599     stf.spill [temp1]=f28,32
0600     stf.spill [temp2]=f29,32
0601     ;;
0602     stf.spill [temp1]=f30,SW(B2)-SW(F30)
0603     stf.spill [temp2]=f31,SW(B3)-SW(F31)
0604     mov temp3=b2
0605     mov temp4=b3
0606     ;;
0607     st8 [temp1]=temp3,16    // save b2
0608     st8 [temp2]=temp4,16    // save b3
0609     mov temp3=b4
0610     mov temp4=b5
0611     ;;
0612     st8 [temp1]=temp3,SW(AR_LC)-SW(B4)  // save b4
0613     st8 [temp2]=temp4   // save b5
0614     mov temp3=ar.lc
0615     ;;
0616     st8 [temp1]=temp3   // save ar.lc
0617 
0618     // FIXME: Some proms are incorrectly accessing the minstate area as
0619     // cached data.  The C code uses region 6, uncached virtual.  Ensure
0620     // that there is no cache data lying around for the first 1K of the
0621     // minstate area.
0622     // Remove this code in September 2006, that gives platforms a year to
0623     // fix their proms and get their customers updated.
0624 
0625     add r1=32*1,r17
0626     add r2=32*2,r17
0627     add r3=32*3,r17
0628     add r4=32*4,r17
0629     add r5=32*5,r17
0630     add r6=32*6,r17
0631     add r7=32*7,r17
0632     ;;
0633     fc r17
0634     fc r1
0635     fc r2
0636     fc r3
0637     fc r4
0638     fc r5
0639     fc r6
0640     fc r7
0641     add r17=32*8,r17
0642     add r1=32*8,r1
0643     add r2=32*8,r2
0644     add r3=32*8,r3
0645     add r4=32*8,r4
0646     add r5=32*8,r5
0647     add r6=32*8,r6
0648     add r7=32*8,r7
0649     ;;
0650     fc r17
0651     fc r1
0652     fc r2
0653     fc r3
0654     fc r4
0655     fc r5
0656     fc r6
0657     fc r7
0658     add r17=32*8,r17
0659     add r1=32*8,r1
0660     add r2=32*8,r2
0661     add r3=32*8,r3
0662     add r4=32*8,r4
0663     add r5=32*8,r5
0664     add r6=32*8,r6
0665     add r7=32*8,r7
0666     ;;
0667     fc r17
0668     fc r1
0669     fc r2
0670     fc r3
0671     fc r4
0672     fc r5
0673     fc r6
0674     fc r7
0675     add r17=32*8,r17
0676     add r1=32*8,r1
0677     add r2=32*8,r2
0678     add r3=32*8,r3
0679     add r4=32*8,r4
0680     add r5=32*8,r5
0681     add r6=32*8,r6
0682     add r7=32*8,r7
0683     ;;
0684     fc r17
0685     fc r1
0686     fc r2
0687     fc r3
0688     fc r4
0689     fc r5
0690     fc r6
0691     fc r7
0692 
0693     br.sptk b0
0694 
0695 //EndStub//////////////////////////////////////////////////////////////////////
0696 
0697 
0698 //++
0699 // Name:
0700 //  ia64_state_restore()
0701 //
0702 // Stub Description:
0703 //
0704 //  Restore the SAL/OS state.  This is sensitive to the layout of struct
0705 //  ia64_sal_os_state in mca.h.
0706 //
0707 //  r2 contains the return address, r3 contains either
0708 //  IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
0709 //
0710 //  In addition to the SAL to OS state, this routine restores all the
0711 //  registers that appear in struct pt_regs and struct switch_stack,
0712 //  excluding those in the PAL minstate area.
0713 //
0714 //--
0715 
0716 ia64_state_restore:
0717     // Restore the switch_stack data that is not in minstate nor pt_regs.
0718     add regs=MCA_SWITCH_STACK_OFFSET, r3
0719     mov b0=r2       // save return address
0720     ;;
0721     GET_IA64_MCA_DATA(temp2)
0722     ;;
0723     add regs=temp2, regs
0724     ;;
0725     add temp1=SW(F2), regs
0726     add temp2=SW(F3), regs
0727     ;;
0728     ldf.fill f2=[temp1],32
0729     ldf.fill f3=[temp2],32
0730     ;;
0731     ldf.fill f4=[temp1],32
0732     ldf.fill f5=[temp2],32
0733     ;;
0734     ldf.fill f12=[temp1],32
0735     ldf.fill f13=[temp2],32
0736     ;;
0737     ldf.fill f14=[temp1],32
0738     ldf.fill f15=[temp2],32
0739     ;;
0740     ldf.fill f16=[temp1],32
0741     ldf.fill f17=[temp2],32
0742     ;;
0743     ldf.fill f18=[temp1],32
0744     ldf.fill f19=[temp2],32
0745     ;;
0746     ldf.fill f20=[temp1],32
0747     ldf.fill f21=[temp2],32
0748     ;;
0749     ldf.fill f22=[temp1],32
0750     ldf.fill f23=[temp2],32
0751     ;;
0752     ldf.fill f24=[temp1],32
0753     ldf.fill f25=[temp2],32
0754     ;;
0755     ldf.fill f26=[temp1],32
0756     ldf.fill f27=[temp2],32
0757     ;;
0758     ldf.fill f28=[temp1],32
0759     ldf.fill f29=[temp2],32
0760     ;;
0761     ldf.fill f30=[temp1],SW(B2)-SW(F30)
0762     ldf.fill f31=[temp2],SW(B3)-SW(F31)
0763     ;;
0764     ld8 temp3=[temp1],16    // restore b2
0765     ld8 temp4=[temp2],16    // restore b3
0766     ;;
0767     mov b2=temp3
0768     mov b3=temp4
0769     ld8 temp3=[temp1],SW(AR_LC)-SW(B4)  // restore b4
0770     ld8 temp4=[temp2]   // restore b5
0771     ;;
0772     mov b4=temp3
0773     mov b5=temp4
0774     ld8 temp3=[temp1]   // restore ar.lc
0775     ;;
0776     mov ar.lc=temp3
0777 
0778     // Restore the pt_regs data that is not in minstate.  The previous code
0779     // left regs at switch_stack.
0780     add regs=MCA_PT_REGS_OFFSET-MCA_SWITCH_STACK_OFFSET, regs
0781     ;;
0782     add temp1=PT(B6), regs
0783     add temp2=PT(B7), regs
0784     ;;
0785     ld8 temp3=[temp1],PT(AR_CSD)-PT(B6)     // restore b6
0786     ld8 temp4=[temp2],PT(AR_SSD)-PT(B7)     // restore b7
0787     ;;
0788     mov b6=temp3
0789     mov b7=temp4
0790     ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD)    // restore ar.csd
0791     ld8 temp4=[temp2],PT(AR_PFS)-PT(AR_SSD)     // restore ar.ssd
0792     ;;
0793     mov ar.csd=temp3
0794     mov ar.ssd=temp4
0795     ld8 temp3=[temp1]               // restore ar.unat
0796     add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
0797     ld8 temp4=[temp2],PT(AR_FPSR)-PT(AR_PFS)    // restore ar.pfs
0798     ;;
0799     mov ar.unat=temp3
0800     mov ar.pfs=temp4
0801     // ar.rnat, ar.bspstore, loadrs are restore in ia64_old_stack.
0802     ld8 temp3=[temp1],PT(F6)-PT(AR_CCV)     // restore ar.ccv
0803     ld8 temp4=[temp2],PT(F7)-PT(AR_FPSR)        // restore ar.fpsr
0804     ;;
0805     mov ar.ccv=temp3
0806     mov ar.fpsr=temp4
0807     ldf.fill f6=[temp1],PT(F8)-PT(F6)
0808     ldf.fill f7=[temp2],PT(F9)-PT(F7)
0809     ;;
0810     ldf.fill f8=[temp1],PT(F10)-PT(F8)
0811     ldf.fill f9=[temp2],PT(F11)-PT(F9)
0812     ;;
0813     ldf.fill f10=[temp1]
0814     ldf.fill f11=[temp2]
0815 
0816     // Restore the SAL to OS state. The previous code left regs at pt_regs.
0817     add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs
0818     ;;
0819     add temp1=SOS(SAL_RA), regs
0820     add temp2=SOS(SAL_GP), regs
0821     ;;
0822     ld8 r12=[temp1],16  // sal_ra
0823     ld8 r9=[temp2],16   // sal_gp
0824     ;;
0825     ld8 r22=[temp1],16  // pal_min_state, virtual
0826     ld8 r13=[temp2],16  // prev_IA64_KR_CURRENT
0827     ;;
0828     ld8 r16=[temp1],16  // prev_IA64_KR_CURRENT_STACK
0829     ld8 r20=[temp2],16  // prev_task
0830     ;;
0831     ld8 temp3=[temp1],16    // cr.isr
0832     ld8 temp4=[temp2],16    // cr.ifa
0833     ;;
0834     mov cr.isr=temp3
0835     mov cr.ifa=temp4
0836     ld8 temp3=[temp1],16    // cr.itir
0837     ld8 temp4=[temp2],16    // cr.iipa
0838     ;;
0839     mov cr.itir=temp3
0840     mov cr.iipa=temp4
0841     ld8 temp3=[temp1]   // cr.iim
0842     ld8 temp4=[temp2]       // cr.iha
0843     add temp1=SOS(OS_STATUS), regs
0844     add temp2=SOS(CONTEXT), regs
0845     ;;
0846     mov cr.iim=temp3
0847     mov cr.iha=temp4
0848     dep r22=0,r22,62,1  // pal_min_state, physical, uncached
0849     mov IA64_KR(CURRENT)=r13
0850     ld8 r8=[temp1]      // os_status
0851     ld8 r10=[temp2]     // context
0852 
0853     /* Wire IA64_TR_CURRENT_STACK to the stack that we are resuming to.  To
0854      * avoid any dependencies on the algorithm in ia64_switch_to(), just
0855      * purge any existing CURRENT_STACK mapping and insert the new one.
0856      *
0857      * r16 contains prev_IA64_KR_CURRENT_STACK, r13 contains
0858      * prev_IA64_KR_CURRENT, these values may have been changed by the C
0859      * code.  Do not use r8, r9, r10, r22, they contain values ready for
0860      * the return to SAL.
0861      */
0862 
0863     mov r15=IA64_KR(CURRENT_STACK)      // physical granule mapped by IA64_TR_CURRENT_STACK
0864     ;;
0865     shl r15=r15,IA64_GRANULE_SHIFT
0866     ;;
0867     dep r15=-1,r15,61,3         // virtual granule
0868     mov r18=IA64_GRANULE_SHIFT<<2       // for cr.itir.ps
0869     ;;
0870     ptr.d r15,r18
0871     ;;
0872     srlz.d
0873 
0874     extr.u r19=r13,61,3         // r13 = prev_IA64_KR_CURRENT
0875     shl r20=r16,IA64_GRANULE_SHIFT      // r16 = prev_IA64_KR_CURRENT_STACK
0876     movl r21=PAGE_KERNEL            // page properties
0877     ;;
0878     mov IA64_KR(CURRENT_STACK)=r16
0879     cmp.ne p6,p0=RGN_KERNEL,r19     // new stack is in the kernel region?
0880     or r21=r20,r21              // construct PA | page properties
0881 (p6)    br.spnt 1f              // the dreaded cpu 0 idle task in region 5:(
0882     ;;
0883     mov cr.itir=r18
0884     mov cr.ifa=r13
0885     mov r20=IA64_TR_CURRENT_STACK
0886     ;;
0887     itr.d dtr[r20]=r21
0888     ;;
0889     srlz.d
0890 1:
0891 
0892     br.sptk b0
0893 
0894 //EndStub//////////////////////////////////////////////////////////////////////
0895 
0896 
0897 //++
0898 // Name:
0899 //  ia64_new_stack()
0900 //
0901 // Stub Description:
0902 //
0903 //  Switch to the MCA/INIT stack.
0904 //
0905 //  r2 contains the return address, r3 contains either
0906 //  IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
0907 //
0908 //  On entry RBS is still on the original stack, this routine switches RBS
0909 //  to use the MCA/INIT stack.
0910 //
0911 //  On entry, sos->pal_min_state is physical, on exit it is virtual.
0912 //
0913 //--
0914 
0915 ia64_new_stack:
0916     add regs=MCA_PT_REGS_OFFSET, r3
0917     add temp2=MCA_SOS_OFFSET+SOS(PAL_MIN_STATE), r3
0918     mov b0=r2           // save return address
0919     GET_IA64_MCA_DATA(temp1)
0920     invala
0921     ;;
0922     add temp2=temp2, temp1      // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
0923     add regs=regs, temp1        // struct pt_regs on MCA or INIT stack
0924     ;;
0925     // Address of minstate area provided by PAL is physical, uncacheable.
0926     // Convert to Linux virtual address in region 6 for C code.
0927     ld8 ms=[temp2]          // pal_min_state, physical
0928     ;;
0929     dep temp1=-1,ms,62,2        // set region 6
0930     mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET
0931     ;;
0932     st8 [temp2]=temp1       // pal_min_state, virtual
0933 
0934     add temp4=temp3, regs       // start of bspstore on new stack
0935     ;;
0936     mov ar.bspstore=temp4       // switch RBS to MCA/INIT stack
0937     ;;
0938     flushrs             // must be first in group
0939     br.sptk b0
0940 
0941 //EndStub//////////////////////////////////////////////////////////////////////
0942 
0943 
0944 //++
0945 // Name:
0946 //  ia64_old_stack()
0947 //
0948 // Stub Description:
0949 //
0950 //  Switch to the old stack.
0951 //
0952 //  r2 contains the return address, r3 contains either
0953 //  IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
0954 //
0955 //  On entry, pal_min_state is virtual, on exit it is physical.
0956 //
0957 //  On entry RBS is on the MCA/INIT stack, this routine switches RBS
0958 //  back to the previous stack.
0959 //
0960 //  The psr is set to all zeroes.  SAL return requires either all zeroes or
0961 //  just psr.mc set.  Leaving psr.mc off allows INIT to be issued if this
0962 //  code does not perform correctly.
0963 //
0964 //  The dirty registers at the time of the event were flushed to the
0965 //  MCA/INIT stack in ia64_pt_regs_save().  Restore the dirty registers
0966 //  before reverting to the previous bspstore.
0967 //--
0968 
0969 ia64_old_stack:
0970     add regs=MCA_PT_REGS_OFFSET, r3
0971     mov b0=r2           // save return address
0972     GET_IA64_MCA_DATA(temp2)
0973     LOAD_PHYSICAL(p0,temp1,1f)
0974     ;;
0975     mov cr.ipsr=r0
0976     mov cr.ifs=r0
0977     mov cr.iip=temp1
0978     ;;
0979     invala
0980     rfi
0981 1:
0982 
0983     add regs=regs, temp2        // struct pt_regs on MCA or INIT stack
0984     ;;
0985     add temp1=PT(LOADRS), regs
0986     ;;
0987     ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS)    // restore loadrs
0988     ;;
0989     ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE)   // restore ar.bspstore
0990     mov ar.rsc=temp2
0991     ;;
0992     loadrs
0993     ld8 temp4=[temp1]       // restore ar.rnat
0994     ;;
0995     mov ar.bspstore=temp3       // back to old stack
0996     ;;
0997     mov ar.rnat=temp4
0998     ;;
0999 
1000     br.sptk b0
1001 
1002 //EndStub//////////////////////////////////////////////////////////////////////
1003 
1004 
1005 //++
1006 // Name:
1007 //  ia64_set_kernel_registers()
1008 //
1009 // Stub Description:
1010 //
1011 //  Set the registers that are required by the C code in order to run on an
1012 //  MCA/INIT stack.
1013 //
1014 //  r2 contains the return address, r3 contains either
1015 //  IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
1016 //
1017 //--
1018 
1019 ia64_set_kernel_registers:
1020     add temp3=MCA_SP_OFFSET, r3
1021     mov b0=r2       // save return address
1022     GET_IA64_MCA_DATA(temp1)
1023     ;;
1024     add r12=temp1, temp3    // kernel stack pointer on MCA/INIT stack
1025     add r13=temp1, r3   // set current to start of MCA/INIT stack
1026     add r20=temp1, r3   // physical start of MCA/INIT stack
1027     ;;
1028     DATA_PA_TO_VA(r12,temp2)
1029     DATA_PA_TO_VA(r13,temp3)
1030     ;;
1031     mov IA64_KR(CURRENT)=r13
1032 
1033     /* Wire IA64_TR_CURRENT_STACK to the MCA/INIT handler stack.  To avoid
1034      * any dependencies on the algorithm in ia64_switch_to(), just purge
1035      * any existing CURRENT_STACK mapping and insert the new one.
1036      */
1037 
1038     mov r16=IA64_KR(CURRENT_STACK)      // physical granule mapped by IA64_TR_CURRENT_STACK
1039     ;;
1040     shl r16=r16,IA64_GRANULE_SHIFT
1041     ;;
1042     dep r16=-1,r16,61,3         // virtual granule
1043     mov r18=IA64_GRANULE_SHIFT<<2       // for cr.itir.ps
1044     ;;
1045     ptr.d r16,r18
1046     ;;
1047     srlz.d
1048 
1049     shr.u r16=r20,IA64_GRANULE_SHIFT    // r20 = physical start of MCA/INIT stack
1050     movl r21=PAGE_KERNEL            // page properties
1051     ;;
1052     mov IA64_KR(CURRENT_STACK)=r16
1053     or r21=r20,r21              // construct PA | page properties
1054     ;;
1055     mov cr.itir=r18
1056     mov cr.ifa=r13
1057     mov r20=IA64_TR_CURRENT_STACK
1058 
1059     movl r17=FPSR_DEFAULT
1060     ;;
1061     mov.m ar.fpsr=r17           // set ar.fpsr to kernel default value
1062     ;;
1063     itr.d dtr[r20]=r21
1064     ;;
1065     srlz.d
1066 
1067     br.sptk b0
1068 
1069 //EndStub//////////////////////////////////////////////////////////////////////
1070 
1071 #undef  ms
1072 #undef  regs
1073 #undef  temp1
1074 #undef  temp2
1075 #undef  temp3
1076 #undef  temp4
1077 
1078 
1079 // Support function for mca.c, it is here to avoid using inline asm.  Given the
1080 // address of an rnat slot, if that address is below the current ar.bspstore
1081 // then return the contents of that slot, otherwise return the contents of
1082 // ar.rnat.
1083 GLOBAL_ENTRY(ia64_get_rnat)
1084     alloc r14=ar.pfs,1,0,0,0
1085     mov ar.rsc=0
1086     ;;
1087     mov r14=ar.bspstore
1088     ;;
1089     cmp.lt p6,p7=in0,r14
1090     ;;
1091 (p6)    ld8 r8=[in0]
1092 (p7)    mov r8=ar.rnat
1093     mov ar.rsc=3
1094     br.ret.sptk.many rp
1095 END(ia64_get_rnat)
1096 
1097 
1098 // void ia64_set_psr_mc(void)
1099 //
1100 // Set psr.mc bit to mask MCA/INIT.
1101 GLOBAL_ENTRY(ia64_set_psr_mc)
1102     rsm psr.i | psr.ic      // disable interrupts
1103     ;;
1104     srlz.d
1105     ;;
1106     mov r14 = psr           // get psr{36:35,31:0}
1107     movl r15 = 1f
1108     ;;
1109     dep r14 = -1, r14, PSR_MC, 1    // set psr.mc
1110     ;;
1111     dep r14 = -1, r14, PSR_IC, 1    // set psr.ic
1112     ;;
1113     dep r14 = -1, r14, PSR_BN, 1    // keep bank1 in use
1114     ;;
1115     mov cr.ipsr = r14
1116     mov cr.ifs = r0
1117     mov cr.iip = r15
1118     ;;
1119     rfi
1120 1:
1121     br.ret.sptk.many rp
1122 END(ia64_set_psr_mc)