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0001 /* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation
0002  *
0003  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
0004  * Written by David Howells (dhowells@redhat.com)
0005  *
0006  * This program is free software; you can redistribute it and/or
0007  * modify it under the terms of the GNU General Public License
0008  * as published by the Free Software Foundation; either version
0009  * 2 of the License, or (at your option) any later version.
0010  */
0011 
0012 #include <linux/init.h>
0013 #include <linux/threads.h>
0014 #include <linux/linkage.h>
0015 #include <asm/ptrace.h>
0016 #include <asm/page.h>
0017 #include <asm/spr-regs.h>
0018 #include <asm/mb86943a.h>
0019 #include "head.inc"
0020 
0021 
0022 #define __400_DBR0  0xfe000e00
0023 #define __400_DBR1  0xfe000e08
0024 #define __400_DBR2  0xfe000e10  /* not on FR401 */
0025 #define __400_DBR3  0xfe000e18  /* not on FR401 */
0026 #define __400_DAM0  0xfe000f00
0027 #define __400_DAM1  0xfe000f08
0028 #define __400_DAM2  0xfe000f10  /* not on FR401 */
0029 #define __400_DAM3  0xfe000f18  /* not on FR401 */
0030 #define __400_LGCR  0xfe000010
0031 #define __400_LCR   0xfe000100
0032 #define __400_LSBR  0xfe000c00
0033 
0034     __INIT
0035     .balign     4
0036 
0037 ###############################################################################
0038 #
0039 # describe the position and layout of the SDRAM controller registers
0040 #
0041 #   ENTRY:          EXIT:
0042 # GR5   -           cacheline size
0043 # GR11  -           displacement of 2nd SDRAM addr reg from GR14
0044 # GR12  -           displacement of 3rd SDRAM addr reg from GR14
0045 # GR13  -           displacement of 4th SDRAM addr reg from GR14
0046 # GR14  -           address of 1st SDRAM addr reg
0047 # GR15  -           amount to shift address by to match SDRAM addr reg
0048 # GR26  &__head_reference   [saved]
0049 # GR30  LED address     [saved]
0050 # CC0   -           T if DBR0 is present
0051 # CC1   -           T if DBR1 is present
0052 # CC2   -           T if DBR2 is present (not FR401/FR401A)
0053 # CC3   -           T if DBR3 is present (not FR401/FR401A)
0054 #
0055 ###############################################################################
0056     .globl      __head_fr401_describe_sdram
0057 __head_fr401_describe_sdram:
0058     sethi.p     %hi(__400_DBR0),gr14
0059     setlo       %lo(__400_DBR0),gr14
0060     setlos.p    #__400_DBR1-__400_DBR0,gr11
0061     setlos      #__400_DBR2-__400_DBR0,gr12
0062     setlos.p    #__400_DBR3-__400_DBR0,gr13
0063     setlos      #32,gr5         ; cacheline size
0064     setlos.p    #0,gr15         ; amount to shift addr reg by
0065 
0066     # specify which DBR regs are present
0067     setlos      #0x00ff,gr4
0068     movgs       gr4,cccr
0069     movsg       psr,gr3         ; check for FR401/FR401A
0070     srli        gr3,#25,gr3
0071     subicc      gr3,#0x20>>1,gr0,icc0
0072     bnelr       icc0,#1
0073     setlos      #0x000f,gr4
0074     movgs       gr4,cccr
0075     bralr
0076 
0077 ###############################################################################
0078 #
0079 # rearrange the bus controller registers
0080 #
0081 #   ENTRY:          EXIT:
0082 # GR26  &__head_reference   [saved]
0083 # GR30  LED address     revised LED address
0084 #
0085 ###############################################################################
0086     .globl      __head_fr401_set_busctl
0087 __head_fr401_set_busctl:
0088     sethi.p     %hi(__400_LGCR),gr4
0089     setlo       %lo(__400_LGCR),gr4
0090     sethi.p     %hi(__400_LSBR),gr10
0091     setlo       %lo(__400_LSBR),gr10
0092     sethi.p     %hi(__400_LCR),gr11
0093     setlo       %lo(__400_LCR),gr11
0094 
0095     # set the bus controller
0096     ldi     @(gr4,#0),gr5
0097     ori     gr5,#0xff,gr5       ; make sure all chip-selects are enabled
0098     sti     gr5,@(gr4,#0)
0099 
0100     sethi.p     %hi(__region_CS1),gr4
0101     setlo       %lo(__region_CS1),gr4
0102     sethi.p     %hi(__region_CS1_M),gr5
0103     setlo       %lo(__region_CS1_M),gr5
0104     sethi.p     %hi(__region_CS1_C),gr6
0105     setlo       %lo(__region_CS1_C),gr6
0106     sti     gr4,@(gr10,#1*0x08)
0107     sti     gr5,@(gr10,#1*0x08+0x100)
0108     sti     gr6,@(gr11,#1*0x08)
0109     sethi.p     %hi(__region_CS2),gr4
0110     setlo       %lo(__region_CS2),gr4
0111     sethi.p     %hi(__region_CS2_M),gr5
0112     setlo       %lo(__region_CS2_M),gr5
0113     sethi.p     %hi(__region_CS2_C),gr6
0114     setlo       %lo(__region_CS2_C),gr6
0115     sti     gr4,@(gr10,#2*0x08)
0116     sti     gr5,@(gr10,#2*0x08+0x100)
0117     sti     gr6,@(gr11,#2*0x08)
0118     sethi.p     %hi(__region_CS3),gr4
0119     setlo       %lo(__region_CS3),gr4
0120     sethi.p     %hi(__region_CS3_M),gr5
0121     setlo       %lo(__region_CS3_M),gr5
0122     sethi.p     %hi(__region_CS3_C),gr6
0123     setlo       %lo(__region_CS3_C),gr6
0124     sti     gr4,@(gr10,#3*0x08)
0125     sti     gr5,@(gr10,#3*0x08+0x100)
0126     sti     gr6,@(gr11,#3*0x08)
0127     sethi.p     %hi(__region_CS4),gr4
0128     setlo       %lo(__region_CS4),gr4
0129     sethi.p     %hi(__region_CS4_M),gr5
0130     setlo       %lo(__region_CS4_M),gr5
0131     sethi.p     %hi(__region_CS4_C),gr6
0132     setlo       %lo(__region_CS4_C),gr6
0133     sti     gr4,@(gr10,#4*0x08)
0134     sti     gr5,@(gr10,#4*0x08+0x100)
0135     sti     gr6,@(gr11,#4*0x08)
0136     sethi.p     %hi(__region_CS5),gr4
0137     setlo       %lo(__region_CS5),gr4
0138     sethi.p     %hi(__region_CS5_M),gr5
0139     setlo       %lo(__region_CS5_M),gr5
0140     sethi.p     %hi(__region_CS5_C),gr6
0141     setlo       %lo(__region_CS5_C),gr6
0142     sti     gr4,@(gr10,#5*0x08)
0143     sti     gr5,@(gr10,#5*0x08+0x100)
0144     sti     gr6,@(gr11,#5*0x08)
0145     sethi.p     %hi(__region_CS6),gr4
0146     setlo       %lo(__region_CS6),gr4
0147     sethi.p     %hi(__region_CS6_M),gr5
0148     setlo       %lo(__region_CS6_M),gr5
0149     sethi.p     %hi(__region_CS6_C),gr6
0150     setlo       %lo(__region_CS6_C),gr6
0151     sti     gr4,@(gr10,#6*0x08)
0152     sti     gr5,@(gr10,#6*0x08+0x100)
0153     sti     gr6,@(gr11,#6*0x08)
0154     sethi.p     %hi(__region_CS7),gr4
0155     setlo       %lo(__region_CS7),gr4
0156     sethi.p     %hi(__region_CS7_M),gr5
0157     setlo       %lo(__region_CS7_M),gr5
0158     sethi.p     %hi(__region_CS7_C),gr6
0159     setlo       %lo(__region_CS7_C),gr6
0160     sti     gr4,@(gr10,#7*0x08)
0161     sti     gr5,@(gr10,#7*0x08+0x100)
0162     sti     gr6,@(gr11,#7*0x08)
0163     membar
0164     bar
0165 
0166     # adjust LED bank address
0167     sethi.p     %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
0168     setlo       %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
0169     bralr
0170 
0171 ###############################################################################
0172 #
0173 # determine the total SDRAM size
0174 #
0175 #   ENTRY:          EXIT:
0176 # GR25  -           SDRAM size
0177 # GR26  &__head_reference   [saved]
0178 # GR30  LED address     [saved]
0179 #
0180 ###############################################################################
0181     .globl      __head_fr401_survey_sdram
0182 __head_fr401_survey_sdram:
0183     sethi.p     %hi(__400_DAM0),gr11
0184     setlo       %lo(__400_DAM0),gr11
0185     sethi.p     %hi(__400_DBR0),gr12
0186     setlo       %lo(__400_DBR0),gr12
0187 
0188     sethi.p     %hi(0xfe000000),gr17        ; unused SDRAM DBR value
0189     setlo       %lo(0xfe000000),gr17
0190     setlos      #0,gr25
0191 
0192     ldi     @(gr12,#0x00),gr4       ; DAR0
0193     subcc       gr4,gr17,gr0,icc0
0194     beq     icc0,#0,__head_no_DCS0
0195     ldi     @(gr11,#0x00),gr6       ; DAM0: bits 31:20 match addr 31:20
0196     add     gr25,gr6,gr25
0197     addi        gr25,#1,gr25
0198 __head_no_DCS0:
0199 
0200     ldi     @(gr12,#0x08),gr4       ; DAR1
0201     subcc       gr4,gr17,gr0,icc0
0202     beq     icc0,#0,__head_no_DCS1
0203     ldi     @(gr11,#0x08),gr6       ; DAM1: bits 31:20 match addr 31:20
0204     add     gr25,gr6,gr25
0205     addi        gr25,#1,gr25
0206 __head_no_DCS1:
0207 
0208     # FR401/FR401A does not have DCS2/3
0209     movsg       psr,gr3
0210     srli        gr3,#25,gr3
0211     subicc      gr3,#0x20>>1,gr0,icc0
0212     beq     icc0,#0,__head_no_DCS3
0213 
0214     ldi     @(gr12,#0x10),gr4       ; DAR2
0215     subcc       gr4,gr17,gr0,icc0
0216     beq     icc0,#0,__head_no_DCS2
0217     ldi     @(gr11,#0x10),gr6       ; DAM2: bits 31:20 match addr 31:20
0218     add     gr25,gr6,gr25
0219     addi        gr25,#1,gr25
0220 __head_no_DCS2:
0221 
0222     ldi     @(gr12,#0x18),gr4       ; DAR3
0223     subcc       gr4,gr17,gr0,icc0
0224     beq     icc0,#0,__head_no_DCS3
0225     ldi     @(gr11,#0x18),gr6       ; DAM3: bits 31:20 match addr 31:20
0226     add     gr25,gr6,gr25
0227     addi        gr25,#1,gr25
0228 __head_no_DCS3:
0229     bralr
0230 
0231 ###############################################################################
0232 #
0233 # set the protection map with the I/DAMPR registers
0234 #
0235 #   ENTRY:          EXIT:
0236 # GR25  SDRAM size      [saved]
0237 # GR26  &__head_reference   [saved]
0238 # GR30  LED address     [saved]
0239 #
0240 ###############################################################################
0241     .globl      __head_fr401_set_protection
0242 __head_fr401_set_protection:
0243     movsg       lr,gr27
0244 
0245     # set the I/O region protection registers for FR401/3/5
0246     sethi.p     %hi(__region_IO),gr5
0247     setlo       %lo(__region_IO),gr5
0248     ori     gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
0249     movgs       gr0,iampr7
0250     movgs       gr5,dampr7          ; General I/O tile
0251 
0252     # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
0253     # - start with the highest numbered registers
0254     sethi.p     %hi(__kernel_image_end),gr8
0255     setlo       %lo(__kernel_image_end),gr8
0256     sethi.p     %hi(32768),gr4          ; allow for a maximal allocator bitmap
0257     setlo       %lo(32768),gr4
0258     add     gr8,gr4,gr8
0259     sethi.p     %hi(1024*2048-1),gr4        ; round up to nearest 2MiB
0260     setlo       %lo(1024*2048-1),gr4
0261     add.p       gr8,gr4,gr8
0262     not     gr4,gr4
0263     and     gr8,gr4,gr8
0264 
0265     sethi.p     %hi(__page_offset),gr9
0266     setlo       %lo(__page_offset),gr9
0267     add     gr9,gr25,gr9
0268 
0269     # GR8 = base of uncovered RAM
0270     # GR9 = top of uncovered RAM
0271 
0272 #ifdef CONFIG_MB93093_PDK
0273     sethi.p     %hi(__region_CS2),gr4
0274     setlo       %lo(__region_CS2),gr4
0275     ori     gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4
0276     movgs       gr4,dampr6
0277     movgs       gr0,iampr6
0278 #else
0279     call        __head_split_region
0280     movgs       gr4,iampr6
0281     movgs       gr5,dampr6
0282 #endif
0283     call        __head_split_region
0284     movgs       gr4,iampr5
0285     movgs       gr5,dampr5
0286     call        __head_split_region
0287     movgs       gr4,iampr4
0288     movgs       gr5,dampr4
0289     call        __head_split_region
0290     movgs       gr4,iampr3
0291     movgs       gr5,dampr3
0292     call        __head_split_region
0293     movgs       gr4,iampr2
0294     movgs       gr5,dampr2
0295     call        __head_split_region
0296     movgs       gr4,iampr1
0297     movgs       gr5,dampr1
0298 
0299     # cover kernel core image with kernel-only segment
0300     sethi.p     %hi(__page_offset),gr8
0301     setlo       %lo(__page_offset),gr8
0302     call        __head_split_region
0303 
0304 #ifdef CONFIG_PROTECT_KERNEL
0305     ori.p       gr4,#xAMPRx_S_KERNEL,gr4
0306     ori     gr5,#xAMPRx_S_KERNEL,gr5
0307 #endif
0308 
0309     movgs       gr4,iampr0
0310     movgs       gr5,dampr0
0311     jmpl        @(gr27,gr0)