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0001 /*
0002  * DRAM/SDRAM initialization - alter with care
0003  * This file is intended to be included from other assembler files
0004  *
0005  * Note: This file may not modify r8 or r9 because they are used to
0006  * carry information from the decompressor to the kernel
0007  *
0008  * Copyright (C) 2000-2007 Axis Communications AB
0009  *
0010  * Authors:  Mikael Starvik <starvik@axis.com>
0011  */
0012 
0013 /* Just to be certain the config file is included, we include it here
0014  * explicitly instead of depending on it being included in the file that
0015  * uses this code.
0016  */
0017 
0018 #include <hwregs/asm/reg_map_asm.h>
0019 #include <hwregs/asm/bif_core_defs_asm.h>
0020 
0021     ;; WARNING! The registers r8 and r9 are used as parameters carrying
0022     ;; information from the decompressor (if the kernel was compressed).
0023     ;; They should not be used in the code below.
0024 
0025     ; Refer to BIF MDS for a description of SDRAM initialization
0026 
0027     ; Bank configuration
0028     move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
0029     move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
0030     move.d   $r1, [$r0]
0031     move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
0032     move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
0033     move.d   $r1, [$r0]
0034 
0035     ; Calculate value of mrs_data
0036     ; CAS latency = 2 && bus_width = 32 => 0x40
0037     ; CAS latency = 3 && bus_width = 32 => 0x60
0038     ; CAS latency = 2 && bus_width = 16 => 0x20
0039     ; CAS latency = 3 && bus_width = 16 => 0x30
0040 
0041     ; Check if value is already supplied in kernel config
0042     move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
0043     bne  _set_timing
0044     nop
0045 
0046     move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
0047     move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
0048     and.d    0x07, $r1       ; Get CAS latency
0049     cmpq     2, $r1      ; CL = 2 ?
0050     beq  _bw_check
0051     nop
0052     move.d   0x60, $r4
0053 
0054 _bw_check:
0055     ; Assume that group 0 width is equal to group 1. This assumption
0056     ; is wrong for a group 1 only hardware (such as the grand old
0057     ; StorPoint+).
0058     move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
0059     and.d    0x200, $r1 ; DRAM width is bit 9
0060     beq      _set_timing
0061     lslq     2, $r4     ;  mrs_data starts at bit 2
0062     lsrq     1, $r4     ;  16 bits. Shift down value.
0063 
0064     ; Set timing parameters (refresh off to avoid Guinness TR 83)
0065 _set_timing:
0066     move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
0067     and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
0068     move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
0069     move.d   $r1, [$r0]
0070 
0071     ; Issue NOP command
0072     move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
0073     moveq regk_bif_core_nop, $r1
0074     move.d $r1, [$r5]
0075 
0076     ; Wait 200us
0077     move.d   10000, $r2
0078 1:  bne      1b
0079     subq     1, $r2
0080 
0081     ; Issue initialization command sequence
0082     lapc     _sdram_commands_start, $r2
0083     lapc     _sdram_commands_end,  $r3
0084 1:  clear.d  $r6
0085     move.b   [$r2+], $r6    ; Load command
0086     or.d     $r4, $r6   ; Add calculated mrs
0087     move.d   $r6, [$r5] ; Write rw_sdram_cmd
0088     ; Wait 80 ns between each command
0089     move.d   4000, $r7
0090 2:  bne  2b
0091     subq     1, $r7
0092     cmp.d    $r2, $r3   ; Last command?
0093     bne      1b
0094     nop
0095 
0096     ; Start refresh
0097     move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
0098     move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
0099     move.d   $r1, [$r0]
0100 
0101     ; Initialization finished
0102     ba       _sdram_commands_end
0103     nop
0104 
0105 _sdram_commands_start:
0106     .byte   regk_bif_core_pre ; Precharge
0107     .byte   regk_bif_core_ref ; refresh
0108     .byte   regk_bif_core_ref ; refresh
0109     .byte   regk_bif_core_ref ; refresh
0110     .byte   regk_bif_core_ref ; refresh
0111     .byte   regk_bif_core_ref ; refresh
0112     .byte   regk_bif_core_ref ; refresh
0113     .byte   regk_bif_core_ref ; refresh
0114     .byte   regk_bif_core_ref ; refresh
0115     .byte   regk_bif_core_mrs ; mrs
0116 _sdram_commands_end: