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0001 /*
0002  * DDR SDRAM initialization - alter with care
0003  * This file is intended to be included from other assembler files
0004  *
0005  * Note: This file may not modify r8 or r9 because they are used to
0006  * carry information from the decompressor to the kernel
0007  *
0008  * Copyright (C) 2005-2007 Axis Communications AB
0009  *
0010  * Authors:  Mikael Starvik <starvik@axis.com>
0011  */
0012 
0013 /* Just to be certain the config file is included, we include it here
0014  * explicitly instead of depending on it being included in the file that
0015  * uses this code.
0016  */
0017 
0018 #include <hwregs/asm/reg_map_asm.h>
0019 #include <hwregs/asm/ddr2_defs_asm.h>
0020 
0021     ;; WARNING! The registers r8 and r9 are used as parameters carrying
0022     ;; information from the decompressor (if the kernel was compressed).
0023     ;; They should not be used in the code below.
0024 
0025     ;; Refer to ddr2 MDS for initialization sequence
0026 
0027     ; 2. Wait 200us
0028     move.d   10000, $r2
0029 1:  bne      1b
0030     subq     1, $r2
0031 
0032     ; Start clock
0033     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
0034     move.d   REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
0035     move.d   $r1, [$r0]
0036 
0037     ; 2. Wait 200us
0038     move.d   10000, $r2
0039 1:  bne      1b
0040     subq     1, $r2
0041 
0042     ; Reset phy and start calibration
0043     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
0044     move.d   REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
0045          REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
0046     move.d   $r1, [$r0]
0047     move.d   REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
0048     move.d   $r1, [$r0]
0049 
0050     ; 2. Wait 200us
0051     move.d   10000, $r2
0052 1:  bne      1b
0053     subq     1, $r2
0054 
0055     ; Issue commands
0056     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
0057     move.d   sdram_commands_start, $r2
0058 command_loop:
0059     movu.b  [$r2+], $r1
0060     movu.w  [$r2+], $r3
0061 do_cmd:
0062     lslq     16, $r1
0063     or.d     $r3, $r1
0064     move.d   $r1, [$r0]
0065     ; 2. Wait 200us
0066     move.d   10000, $r4
0067 1:  bne      1b
0068     subq     1, $r4
0069     cmp.d    sdram_commands_end, $r2
0070     blo      command_loop
0071     nop
0072 
0073     ; Set timing
0074     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
0075     move.d   CONFIG_ETRAX_DDR2_TIMING, $r1
0076     move.d   $r1, [$r0]
0077 
0078     ; Set latency
0079     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
0080     move.d   CONFIG_ETRAX_DDR2_LATENCY, $r1
0081     move.d   $r1, [$r0]
0082 
0083     ; Set configuration
0084     move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
0085     move.d   CONFIG_ETRAX_DDR2_CONFIG, $r1
0086     move.d   $r1, [$r0]
0087 
0088     ba after_sdram_commands
0089     nop
0090 
0091 sdram_commands_start:
0092     .byte regk_ddr2_deselect
0093     .word 0
0094     .byte regk_ddr2_pre
0095     .word regk_ddr2_pre_all
0096     .byte regk_ddr2_emrs2
0097     .word 0
0098     .byte regk_ddr2_emrs3
0099     .word 0
0100     .byte regk_ddr2_emrs
0101     .word regk_ddr2_dll_en
0102     .byte regk_ddr2_mrs
0103     .word regk_ddr2_dll_rst
0104     .byte regk_ddr2_pre
0105     .word regk_ddr2_pre_all
0106     .byte regk_ddr2_ref
0107     .word 0
0108     .byte regk_ddr2_ref
0109     .word 0
0110     .byte regk_ddr2_mrs
0111     .word CONFIG_ETRAX_DDR2_MRS & 0xffff
0112     .byte regk_ddr2_emrs
0113     .word regk_ddr2_ocd_default | regk_ddr2_dll_en
0114     .byte regk_ddr2_emrs
0115     .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
0116 sdram_commands_end:
0117     .align 1
0118 after_sdram_commands: