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0001 /*
0002  * ARC CPU startup Code
0003  *
0004  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License version 2 as
0008  * published by the Free Software Foundation.
0009  *
0010  * Vineetg: Dec 2007
0011  *  -Check if we are running on Simulator or on real hardware
0012  *      to skip certain things during boot on simulator
0013  */
0014 
0015 #include <linux/linkage.h>
0016 #include <asm/asm-offsets.h>
0017 #include <asm/entry.h>
0018 #include <asm/arcregs.h>
0019 #include <asm/cache.h>
0020 
0021 .macro CPU_EARLY_SETUP
0022 
0023     ; Setting up Vectror Table (in case exception happens in early boot
0024     sr  @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
0025 
0026     ; Disable I-cache/D-cache if kernel so configured
0027     lr  r5, [ARC_REG_IC_BCR]
0028     breq    r5, 0, 1f       ; I$ doesn't exist
0029     lr  r5, [ARC_REG_IC_CTRL]
0030 #ifdef CONFIG_ARC_HAS_ICACHE
0031     bclr    r5, r5, 0       ; 0 - Enable, 1 is Disable
0032 #else
0033     bset    r5, r5, 0       ; I$ exists, but is not used
0034 #endif
0035     sr  r5, [ARC_REG_IC_CTRL]
0036 
0037 1:
0038     lr  r5, [ARC_REG_DC_BCR]
0039     breq    r5, 0, 1f       ; D$ doesn't exist
0040     lr  r5, [ARC_REG_DC_CTRL]
0041     bclr    r5, r5, 6       ; Invalidate (discard w/o wback)
0042 #ifdef CONFIG_ARC_HAS_DCACHE
0043     bclr    r5, r5, 0       ; Enable (+Inv)
0044 #else
0045     bset    r5, r5, 0       ; Disable (+Inv)
0046 #endif
0047     sr  r5, [ARC_REG_DC_CTRL]
0048 
0049 1:
0050 .endm
0051 
0052     .section .init.text, "ax",@progbits
0053 
0054 ;----------------------------------------------------------------
0055 ; Default Reset Handler (jumped into from Reset vector)
0056 ; - Don't clobber r0,r1,r2 as they might have u-boot provided args
0057 ; - Platforms can override this weak version if needed
0058 ;----------------------------------------------------------------
0059 WEAK(res_service)
0060     j   stext
0061 END(res_service)
0062 
0063 ;----------------------------------------------------------------
0064 ; Kernel Entry point
0065 ;----------------------------------------------------------------
0066 ENTRY(stext)
0067 
0068     CPU_EARLY_SETUP
0069 
0070 #ifdef CONFIG_SMP
0071     GET_CPU_ID  r5
0072     cmp r5, 0
0073     mov.nz  r0, r5
0074     bz  .Lmaster_proceed
0075 
0076     ; Non-Masters wait for Master to boot enough and bring them up
0077     ; when they resume, tail-call to entry point
0078     mov blink, @first_lines_of_secondary
0079     j   arc_platform_smp_wait_to_boot
0080 
0081 .Lmaster_proceed:
0082 #endif
0083 
0084     ; Clear BSS before updating any globals
0085     ; XXX: use ZOL here
0086     mov r5, __bss_start
0087     sub r6, __bss_stop, r5
0088     lsr.f   lp_count, r6, 2
0089     lpnz    1f
0090     st.ab   0, [r5, 4]
0091 1:
0092 
0093 #ifdef CONFIG_ARC_UBOOT_SUPPORT
0094     ; Uboot - kernel ABI
0095     ;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
0096     ;    r1 = magic number (board identity, unused as of now
0097     ;    r2 = pointer to uboot provided cmdline or external DTB in mem
0098     ; These are handled later in setup_arch()
0099     st  r0, [@uboot_tag]
0100     st  r2, [@uboot_arg]
0101 #endif
0102 
0103     ; setup "current" tsk and optionally cache it in dedicated r25
0104     mov r9, @init_task
0105     SET_CURR_TASK_ON_CPU  r9, r0    ; r9 = tsk, r0 = scratch
0106 
0107     ; setup stack (fp, sp)
0108     mov fp, 0
0109 
0110     ; tsk->thread_info is really a PAGE, whose bottom hoists stack
0111     GET_TSK_STACK_BASE r9, sp   ; r9 = tsk, sp = stack base(output)
0112 
0113     j   start_kernel    ; "C" entry point
0114 END(stext)
0115 
0116 #ifdef CONFIG_SMP
0117 ;----------------------------------------------------------------
0118 ;     First lines of code run by secondary before jumping to 'C'
0119 ;----------------------------------------------------------------
0120     .section .text, "ax",@progbits
0121 ENTRY(first_lines_of_secondary)
0122 
0123     ; setup per-cpu idle task as "current" on this CPU
0124     ld  r0, [@secondary_idle_tsk]
0125     SET_CURR_TASK_ON_CPU  r0, r1
0126 
0127     ; setup stack (fp, sp)
0128     mov fp, 0
0129 
0130     ; set it's stack base to tsk->thread_info bottom
0131     GET_TSK_STACK_BASE r0, sp
0132 
0133     j   start_kernel_secondary
0134 END(first_lines_of_secondary)
0135 #endif