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0001 PINCTRL (PIN CONTROL) subsystem
0002 This document outlines the pin control subsystem in Linux
0003 
0004 This subsystem deals with:
0005 
0006 - Enumerating and naming controllable pins
0007 
0008 - Multiplexing of pins, pads, fingers (etc) see below for details
0009 
0010 - Configuration of pins, pads, fingers (etc), such as software-controlled
0011   biasing and driving mode specific pins, such as pull-up/down, open drain,
0012   load capacitance etc.
0013 
0014 Top-level interface
0015 ===================
0016 
0017 Definition of PIN CONTROLLER:
0018 
0019 - A pin controller is a piece of hardware, usually a set of registers, that
0020   can control PINs. It may be able to multiplex, bias, set load capacitance,
0021   set drive strength, etc. for individual pins or groups of pins.
0022 
0023 Definition of PIN:
0024 
0025 - PINS are equal to pads, fingers, balls or whatever packaging input or
0026   output line you want to control and these are denoted by unsigned integers
0027   in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
0028   there may be several such number spaces in a system. This pin space may
0029   be sparse - i.e. there may be gaps in the space with numbers where no
0030   pin exists.
0031 
0032 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
0033 pin control framework, and this descriptor contains an array of pin descriptors
0034 describing the pins handled by this specific pin controller.
0035 
0036 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
0037 
0038         A   B   C   D   E   F   G   H
0039 
0040    8    o   o   o   o   o   o   o   o
0041 
0042    7    o   o   o   o   o   o   o   o
0043 
0044    6    o   o   o   o   o   o   o   o
0045 
0046    5    o   o   o   o   o   o   o   o
0047 
0048    4    o   o   o   o   o   o   o   o
0049 
0050    3    o   o   o   o   o   o   o   o
0051 
0052    2    o   o   o   o   o   o   o   o
0053 
0054    1    o   o   o   o   o   o   o   o
0055 
0056 To register a pin controller and name all the pins on this package we can do
0057 this in our driver:
0058 
0059 #include <linux/pinctrl/pinctrl.h>
0060 
0061 const struct pinctrl_pin_desc foo_pins[] = {
0062       PINCTRL_PIN(0, "A8"),
0063       PINCTRL_PIN(1, "B8"),
0064       PINCTRL_PIN(2, "C8"),
0065       ...
0066       PINCTRL_PIN(61, "F1"),
0067       PINCTRL_PIN(62, "G1"),
0068       PINCTRL_PIN(63, "H1"),
0069 };
0070 
0071 static struct pinctrl_desc foo_desc = {
0072         .name = "foo",
0073         .pins = foo_pins,
0074         .npins = ARRAY_SIZE(foo_pins),
0075         .owner = THIS_MODULE,
0076 };
0077 
0078 int __init foo_probe(void)
0079 {
0080         struct pinctrl_dev *pctl;
0081 
0082         pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
0083         if (!pctl)
0084                 pr_err("could not register foo pin driver\n");
0085 }
0086 
0087 To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
0088 selected drivers, you need to select them from your machine's Kconfig entry,
0089 since these are so tightly integrated with the machines they are used on.
0090 See for example arch/arm/mach-u300/Kconfig for an example.
0091 
0092 Pins usually have fancier names than this. You can find these in the datasheet
0093 for your chip. Notice that the core pinctrl.h file provides a fancy macro
0094 called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
0095 the pins from 0 in the upper left corner to 63 in the lower right corner.
0096 This enumeration was arbitrarily chosen, in practice you need to think
0097 through your numbering system so that it matches the layout of registers
0098 and such things in your driver, or the code may become complicated. You must
0099 also consider matching of offsets to the GPIO ranges that may be handled by
0100 the pin controller.
0101 
0102 For a padring with 467 pads, as opposed to actual pins, I used an enumeration
0103 like this, walking around the edge of the chip, which seems to be industry
0104 standard too (all these pads had names, too):
0105 
0106 
0107      0 ..... 104
0108    466        105
0109      .        .
0110      .        .
0111    358        224
0112     357 .... 225
0113 
0114 
0115 Pin groups
0116 ==========
0117 
0118 Many controllers need to deal with groups of pins, so the pin controller
0119 subsystem has a mechanism for enumerating groups of pins and retrieving the
0120 actual enumerated pins that are part of a certain group.
0121 
0122 For example, say that we have a group of pins dealing with an SPI interface
0123 on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
0124 on { 24, 25 }.
0125 
0126 These two groups are presented to the pin control subsystem by implementing
0127 some generic pinctrl_ops like this:
0128 
0129 #include <linux/pinctrl/pinctrl.h>
0130 
0131 struct foo_group {
0132         const char *name;
0133         const unsigned int *pins;
0134         const unsigned num_pins;
0135 };
0136 
0137 static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
0138 static const unsigned int i2c0_pins[] = { 24, 25 };
0139 
0140 static const struct foo_group foo_groups[] = {
0141         {
0142                 .name = "spi0_grp",
0143                 .pins = spi0_pins,
0144                 .num_pins = ARRAY_SIZE(spi0_pins),
0145         },
0146         {
0147                 .name = "i2c0_grp",
0148                 .pins = i2c0_pins,
0149                 .num_pins = ARRAY_SIZE(i2c0_pins),
0150         },
0151 };
0152 
0153 
0154 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
0155 {
0156         return ARRAY_SIZE(foo_groups);
0157 }
0158 
0159 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
0160                                        unsigned selector)
0161 {
0162         return foo_groups[selector].name;
0163 }
0164 
0165 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
0166                                const unsigned **pins,
0167                                unsigned *num_pins)
0168 {
0169         *pins = (unsigned *) foo_groups[selector].pins;
0170         *num_pins = foo_groups[selector].num_pins;
0171         return 0;
0172 }
0173 
0174 static struct pinctrl_ops foo_pctrl_ops = {
0175         .get_groups_count = foo_get_groups_count,
0176         .get_group_name = foo_get_group_name,
0177         .get_group_pins = foo_get_group_pins,
0178 };
0179 
0180 
0181 static struct pinctrl_desc foo_desc = {
0182        ...
0183        .pctlops = &foo_pctrl_ops,
0184 };
0185 
0186 The pin control subsystem will call the .get_groups_count() function to
0187 determine the total number of legal selectors, then it will call the other functions
0188 to retrieve the name and pins of the group. Maintaining the data structure of
0189 the groups is up to the driver, this is just a simple example - in practice you
0190 may need more entries in your group structure, for example specific register
0191 ranges associated with each group and so on.
0192 
0193 
0194 Pin configuration
0195 =================
0196 
0197 Pins can sometimes be software-configured in various ways, mostly related
0198 to their electronic properties when used as inputs or outputs. For example you
0199 may be able to make an output pin high impedance, or "tristate" meaning it is
0200 effectively disconnected. You may be able to connect an input pin to VDD or GND
0201 using a certain resistor value - pull up and pull down - so that the pin has a
0202 stable value when nothing is driving the rail it is connected to, or when it's
0203 unconnected.
0204 
0205 Pin configuration can be programmed by adding configuration entries into the
0206 mapping table; see section "Board/machine configuration" below.
0207 
0208 The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
0209 above, is entirely defined by the pin controller driver.
0210 
0211 The pin configuration driver implements callbacks for changing pin
0212 configuration in the pin controller ops like this:
0213 
0214 #include <linux/pinctrl/pinctrl.h>
0215 #include <linux/pinctrl/pinconf.h>
0216 #include "platform_x_pindefs.h"
0217 
0218 static int foo_pin_config_get(struct pinctrl_dev *pctldev,
0219                     unsigned offset,
0220                     unsigned long *config)
0221 {
0222         struct my_conftype conf;
0223 
0224         ... Find setting for pin @ offset ...
0225 
0226         *config = (unsigned long) conf;
0227 }
0228 
0229 static int foo_pin_config_set(struct pinctrl_dev *pctldev,
0230                     unsigned offset,
0231                     unsigned long config)
0232 {
0233         struct my_conftype *conf = (struct my_conftype *) config;
0234 
0235         switch (conf) {
0236                 case PLATFORM_X_PULL_UP:
0237                 ...
0238                 }
0239         }
0240 }
0241 
0242 static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
0243                     unsigned selector,
0244                     unsigned long *config)
0245 {
0246         ...
0247 }
0248 
0249 static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
0250                     unsigned selector,
0251                     unsigned long config)
0252 {
0253         ...
0254 }
0255 
0256 static struct pinconf_ops foo_pconf_ops = {
0257         .pin_config_get = foo_pin_config_get,
0258         .pin_config_set = foo_pin_config_set,
0259         .pin_config_group_get = foo_pin_config_group_get,
0260         .pin_config_group_set = foo_pin_config_group_set,
0261 };
0262 
0263 /* Pin config operations are handled by some pin controller */
0264 static struct pinctrl_desc foo_desc = {
0265         ...
0266         .confops = &foo_pconf_ops,
0267 };
0268 
0269 Since some controllers have special logic for handling entire groups of pins
0270 they can exploit the special whole-group pin control function. The
0271 pin_config_group_set() callback is allowed to return the error code -EAGAIN,
0272 for groups it does not want to handle, or if it just wants to do some
0273 group-level handling and then fall through to iterate over all pins, in which
0274 case each individual pin will be treated by separate pin_config_set() calls as
0275 well.
0276 
0277 
0278 Interaction with the GPIO subsystem
0279 ===================================
0280 
0281 The GPIO drivers may want to perform operations of various types on the same
0282 physical pins that are also registered as pin controller pins.
0283 
0284 First and foremost, the two subsystems can be used as completely orthogonal,
0285 see the section named "pin control requests from drivers" and
0286 "drivers needing both pin control and GPIOs" below for details. But in some
0287 situations a cross-subsystem mapping between pins and GPIOs is needed.
0288 
0289 Since the pin controller subsystem has its pinspace local to the pin controller
0290 we need a mapping so that the pin control subsystem can figure out which pin
0291 controller handles control of a certain GPIO pin. Since a single pin controller
0292 may be muxing several GPIO ranges (typically SoCs that have one set of pins,
0293 but internally several GPIO silicon blocks, each modelled as a struct
0294 gpio_chip) any number of GPIO ranges can be added to a pin controller instance
0295 like this:
0296 
0297 struct gpio_chip chip_a;
0298 struct gpio_chip chip_b;
0299 
0300 static struct pinctrl_gpio_range gpio_range_a = {
0301         .name = "chip a",
0302         .id = 0,
0303         .base = 32,
0304         .pin_base = 32,
0305         .npins = 16,
0306         .gc = &chip_a;
0307 };
0308 
0309 static struct pinctrl_gpio_range gpio_range_b = {
0310         .name = "chip b",
0311         .id = 0,
0312         .base = 48,
0313         .pin_base = 64,
0314         .npins = 8,
0315         .gc = &chip_b;
0316 };
0317 
0318 {
0319         struct pinctrl_dev *pctl;
0320         ...
0321         pinctrl_add_gpio_range(pctl, &gpio_range_a);
0322         pinctrl_add_gpio_range(pctl, &gpio_range_b);
0323 }
0324 
0325 So this complex system has one pin controller handling two different
0326 GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
0327 "chip b" have different .pin_base, which means a start pin number of the
0328 GPIO range.
0329 
0330 The GPIO range of "chip a" starts from the GPIO base of 32 and actual
0331 pin range also starts from 32. However "chip b" has different starting
0332 offset for the GPIO range and pin range. The GPIO range of "chip b" starts
0333 from GPIO number 48, while the pin range of "chip b" starts from 64.
0334 
0335 We can convert a gpio number to actual pin number using this "pin_base".
0336 They are mapped in the global GPIO pin space at:
0337 
0338 chip a:
0339  - GPIO range : [32 .. 47]
0340  - pin range  : [32 .. 47]
0341 chip b:
0342  - GPIO range : [48 .. 55]
0343  - pin range  : [64 .. 71]
0344 
0345 The above examples assume the mapping between the GPIOs and pins is
0346 linear. If the mapping is sparse or haphazard, an array of arbitrary pin
0347 numbers can be encoded in the range like this:
0348 
0349 static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
0350 
0351 static struct pinctrl_gpio_range gpio_range = {
0352         .name = "chip",
0353         .id = 0,
0354         .base = 32,
0355         .pins = &range_pins,
0356         .npins = ARRAY_SIZE(range_pins),
0357         .gc = &chip;
0358 };
0359 
0360 In this case the pin_base property will be ignored. If the name of a pin
0361 group is known, the pins and npins elements of the above structure can be
0362 initialised using the function pinctrl_get_group_pins(), e.g. for pin
0363 group "foo":
0364 
0365 pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
0366 
0367 When GPIO-specific functions in the pin control subsystem are called, these
0368 ranges will be used to look up the appropriate pin controller by inspecting
0369 and matching the pin to the pin ranges across all controllers. When a
0370 pin controller handling the matching range is found, GPIO-specific functions
0371 will be called on that specific pin controller.
0372 
0373 For all functionalities dealing with pin biasing, pin muxing etc, the pin
0374 controller subsystem will look up the corresponding pin number from the passed
0375 in gpio number, and use the range's internals to retrieve a pin number. After
0376 that, the subsystem passes it on to the pin control driver, so the driver
0377 will get a pin number into its handled number range. Further it is also passed
0378 the range ID value, so that the pin controller knows which range it should
0379 deal with.
0380 
0381 Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
0382 section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
0383 pinctrl and gpio drivers.
0384 
0385 
0386 PINMUX interfaces
0387 =================
0388 
0389 These calls use the pinmux_* naming prefix.  No other calls should use that
0390 prefix.
0391 
0392 
0393 What is pinmuxing?
0394 ==================
0395 
0396 PINMUX, also known as padmux, ballmux, alternate functions or mission modes
0397 is a way for chip vendors producing some kind of electrical packages to use
0398 a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
0399 functions, depending on the application. By "application" in this context
0400 we usually mean a way of soldering or wiring the package into an electronic
0401 system, even though the framework makes it possible to also change the function
0402 at runtime.
0403 
0404 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
0405 
0406         A   B   C   D   E   F   G   H
0407       +---+
0408    8  | o | o   o   o   o   o   o   o
0409       |   |
0410    7  | o | o   o   o   o   o   o   o
0411       |   |
0412    6  | o | o   o   o   o   o   o   o
0413       +---+---+
0414    5  | o | o | o   o   o   o   o   o
0415       +---+---+               +---+
0416    4    o   o   o   o   o   o | o | o
0417                               |   |
0418    3    o   o   o   o   o   o | o | o
0419                               |   |
0420    2    o   o   o   o   o   o | o | o
0421       +-------+-------+-------+---+---+
0422    1  | o   o | o   o | o   o | o | o |
0423       +-------+-------+-------+---+---+
0424 
0425 This is not tetris. The game to think of is chess. Not all PGA/BGA packages
0426 are chessboard-like, big ones have "holes" in some arrangement according to
0427 different design patterns, but we're using this as a simple example. Of the
0428 pins you see some will be taken by things like a few VCC and GND to feed power
0429 to the chip, and quite a few will be taken by large ports like an external
0430 memory interface. The remaining pins will often be subject to pin multiplexing.
0431 
0432 The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
0433 to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
0434 pinctrl_register_pins() and a suitable data set as shown earlier.
0435 
0436 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
0437 (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
0438 some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
0439 be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
0440 we cannot use the SPI port and I2C port at the same time. However in the inside
0441 of the package the silicon performing the SPI logic can alternatively be routed
0442 out on pins { G4, G3, G2, G1 }.
0443 
0444 On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
0445 special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
0446 consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
0447 { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
0448 port on pins { G4, G3, G2, G1 } of course.
0449 
0450 This way the silicon blocks present inside the chip can be multiplexed "muxed"
0451 out on different pin ranges. Often contemporary SoC (systems on chip) will
0452 contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
0453 different pins by pinmux settings.
0454 
0455 Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
0456 common to be able to use almost any pin as a GPIO pin if it is not currently
0457 in use by some other I/O port.
0458 
0459 
0460 Pinmux conventions
0461 ==================
0462 
0463 The purpose of the pinmux functionality in the pin controller subsystem is to
0464 abstract and provide pinmux settings to the devices you choose to instantiate
0465 in your machine configuration. It is inspired by the clk, GPIO and regulator
0466 subsystems, so devices will request their mux setting, but it's also possible
0467 to request a single pin for e.g. GPIO.
0468 
0469 Definitions:
0470 
0471 - FUNCTIONS can be switched in and out by a driver residing with the pin
0472   control subsystem in the drivers/pinctrl/* directory of the kernel. The
0473   pin control driver knows the possible functions. In the example above you can
0474   identify three pinmux functions, one for spi, one for i2c and one for mmc.
0475 
0476 - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
0477   In this case the array could be something like: { spi0, i2c0, mmc0 }
0478   for the three available functions.
0479 
0480 - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
0481   function is *always* associated with a certain set of pin groups, could
0482   be just a single one, but could also be many. In the example above the
0483   function i2c is associated with the pins { A5, B5 }, enumerated as
0484   { 24, 25 } in the controller pin space.
0485 
0486   The Function spi is associated with pin groups { A8, A7, A6, A5 }
0487   and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
0488   { 38, 46, 54, 62 } respectively.
0489 
0490   Group names must be unique per pin controller, no two groups on the same
0491   controller may have the same name.
0492 
0493 - The combination of a FUNCTION and a PIN GROUP determine a certain function
0494   for a certain set of pins. The knowledge of the functions and pin groups
0495   and their machine-specific particulars are kept inside the pinmux driver,
0496   from the outside only the enumerators are known, and the driver core can
0497   request:
0498 
0499   - The name of a function with a certain selector (>= 0)
0500   - A list of groups associated with a certain function
0501   - That a certain group in that list to be activated for a certain function
0502 
0503   As already described above, pin groups are in turn self-descriptive, so
0504   the core will retrieve the actual pin range in a certain group from the
0505   driver.
0506 
0507 - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
0508   device by the board file, device tree or similar machine setup configuration
0509   mechanism, similar to how regulators are connected to devices, usually by
0510   name. Defining a pin controller, function and group thus uniquely identify
0511   the set of pins to be used by a certain device. (If only one possible group
0512   of pins is available for the function, no group name need to be supplied -
0513   the core will simply select the first and only group available.)
0514 
0515   In the example case we can define that this particular machine shall
0516   use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
0517   fi2c0 group gi2c0, on the primary pin controller, we get mappings
0518   like these:
0519 
0520   {
0521     {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
0522     {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
0523   }
0524 
0525   Every map must be assigned a state name, pin controller, device and
0526   function. The group is not compulsory - if it is omitted the first group
0527   presented by the driver as applicable for the function will be selected,
0528   which is useful for simple cases.
0529 
0530   It is possible to map several groups to the same combination of device,
0531   pin controller and function. This is for cases where a certain function on
0532   a certain pin controller may use different sets of pins in different
0533   configurations.
0534 
0535 - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
0536   PIN CONTROLLER are provided on a first-come first-serve basis, so if some
0537   other device mux setting or GPIO pin request has already taken your physical
0538   pin, you will be denied the use of it. To get (activate) a new setting, the
0539   old one has to be put (deactivated) first.
0540 
0541 Sometimes the documentation and hardware registers will be oriented around
0542 pads (or "fingers") rather than pins - these are the soldering surfaces on the
0543 silicon inside the package, and may or may not match the actual number of
0544 pins/balls underneath the capsule. Pick some enumeration that makes sense to
0545 you. Define enumerators only for the pins you can control if that makes sense.
0546 
0547 Assumptions:
0548 
0549 We assume that the number of possible function maps to pin groups is limited by
0550 the hardware. I.e. we assume that there is no system where any function can be
0551 mapped to any pin, like in a phone exchange. So the available pin groups for
0552 a certain function will be limited to a few choices (say up to eight or so),
0553 not hundreds or any amount of choices. This is the characteristic we have found
0554 by inspecting available pinmux hardware, and a necessary assumption since we
0555 expect pinmux drivers to present *all* possible function vs pin group mappings
0556 to the subsystem.
0557 
0558 
0559 Pinmux drivers
0560 ==============
0561 
0562 The pinmux core takes care of preventing conflicts on pins and calling
0563 the pin controller driver to execute different settings.
0564 
0565 It is the responsibility of the pinmux driver to impose further restrictions
0566 (say for example infer electronic limitations due to load, etc.) to determine
0567 whether or not the requested function can actually be allowed, and in case it
0568 is possible to perform the requested mux setting, poke the hardware so that
0569 this happens.
0570 
0571 Pinmux drivers are required to supply a few callback functions, some are
0572 optional. Usually the set_mux() function is implemented, writing values into
0573 some certain registers to activate a certain mux setting for a certain pin.
0574 
0575 A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
0576 into some register named MUX to select a certain function with a certain
0577 group of pins would work something like this:
0578 
0579 #include <linux/pinctrl/pinctrl.h>
0580 #include <linux/pinctrl/pinmux.h>
0581 
0582 struct foo_group {
0583         const char *name;
0584         const unsigned int *pins;
0585         const unsigned num_pins;
0586 };
0587 
0588 static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
0589 static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
0590 static const unsigned i2c0_pins[] = { 24, 25 };
0591 static const unsigned mmc0_1_pins[] = { 56, 57 };
0592 static const unsigned mmc0_2_pins[] = { 58, 59 };
0593 static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
0594 
0595 static const struct foo_group foo_groups[] = {
0596         {
0597                 .name = "spi0_0_grp",
0598                 .pins = spi0_0_pins,
0599                 .num_pins = ARRAY_SIZE(spi0_0_pins),
0600         },
0601         {
0602                 .name = "spi0_1_grp",
0603                 .pins = spi0_1_pins,
0604                 .num_pins = ARRAY_SIZE(spi0_1_pins),
0605         },
0606         {
0607                 .name = "i2c0_grp",
0608                 .pins = i2c0_pins,
0609                 .num_pins = ARRAY_SIZE(i2c0_pins),
0610         },
0611         {
0612                 .name = "mmc0_1_grp",
0613                 .pins = mmc0_1_pins,
0614                 .num_pins = ARRAY_SIZE(mmc0_1_pins),
0615         },
0616         {
0617                 .name = "mmc0_2_grp",
0618                 .pins = mmc0_2_pins,
0619                 .num_pins = ARRAY_SIZE(mmc0_2_pins),
0620         },
0621         {
0622                 .name = "mmc0_3_grp",
0623                 .pins = mmc0_3_pins,
0624                 .num_pins = ARRAY_SIZE(mmc0_3_pins),
0625         },
0626 };
0627 
0628 
0629 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
0630 {
0631         return ARRAY_SIZE(foo_groups);
0632 }
0633 
0634 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
0635                                        unsigned selector)
0636 {
0637         return foo_groups[selector].name;
0638 }
0639 
0640 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
0641                                unsigned ** const pins,
0642                                unsigned * const num_pins)
0643 {
0644         *pins = (unsigned *) foo_groups[selector].pins;
0645         *num_pins = foo_groups[selector].num_pins;
0646         return 0;
0647 }
0648 
0649 static struct pinctrl_ops foo_pctrl_ops = {
0650         .get_groups_count = foo_get_groups_count,
0651         .get_group_name = foo_get_group_name,
0652         .get_group_pins = foo_get_group_pins,
0653 };
0654 
0655 struct foo_pmx_func {
0656         const char *name;
0657         const char * const *groups;
0658         const unsigned num_groups;
0659 };
0660 
0661 static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
0662 static const char * const i2c0_groups[] = { "i2c0_grp" };
0663 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
0664                                         "mmc0_3_grp" };
0665 
0666 static const struct foo_pmx_func foo_functions[] = {
0667         {
0668                 .name = "spi0",
0669                 .groups = spi0_groups,
0670                 .num_groups = ARRAY_SIZE(spi0_groups),
0671         },
0672         {
0673                 .name = "i2c0",
0674                 .groups = i2c0_groups,
0675                 .num_groups = ARRAY_SIZE(i2c0_groups),
0676         },
0677         {
0678                 .name = "mmc0",
0679                 .groups = mmc0_groups,
0680                 .num_groups = ARRAY_SIZE(mmc0_groups),
0681         },
0682 };
0683 
0684 static int foo_get_functions_count(struct pinctrl_dev *pctldev)
0685 {
0686         return ARRAY_SIZE(foo_functions);
0687 }
0688 
0689 static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
0690 {
0691         return foo_functions[selector].name;
0692 }
0693 
0694 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
0695                           const char * const **groups,
0696                           unsigned * const num_groups)
0697 {
0698         *groups = foo_functions[selector].groups;
0699         *num_groups = foo_functions[selector].num_groups;
0700         return 0;
0701 }
0702 
0703 static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
0704                 unsigned group)
0705 {
0706         u8 regbit = (1 << selector + group);
0707 
0708         writeb((readb(MUX)|regbit), MUX)
0709         return 0;
0710 }
0711 
0712 static struct pinmux_ops foo_pmxops = {
0713         .get_functions_count = foo_get_functions_count,
0714         .get_function_name = foo_get_fname,
0715         .get_function_groups = foo_get_groups,
0716         .set_mux = foo_set_mux,
0717         .strict = true,
0718 };
0719 
0720 /* Pinmux operations are handled by some pin controller */
0721 static struct pinctrl_desc foo_desc = {
0722         ...
0723         .pctlops = &foo_pctrl_ops,
0724         .pmxops = &foo_pmxops,
0725 };
0726 
0727 In the example activating muxing 0 and 1 at the same time setting bits
0728 0 and 1, uses one pin in common so they would collide.
0729 
0730 The beauty of the pinmux subsystem is that since it keeps track of all
0731 pins and who is using them, it will already have denied an impossible
0732 request like that, so the driver does not need to worry about such
0733 things - when it gets a selector passed in, the pinmux subsystem makes
0734 sure no other device or GPIO assignment is already using the selected
0735 pins. Thus bits 0 and 1 in the control register will never be set at the
0736 same time.
0737 
0738 All the above functions are mandatory to implement for a pinmux driver.
0739 
0740 
0741 Pin control interaction with the GPIO subsystem
0742 ===============================================
0743 
0744 Note that the following implies that the use case is to use a certain pin
0745 from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
0746 and similar functions. There are cases where you may be using something
0747 that your datasheet calls "GPIO mode", but actually is just an electrical
0748 configuration for a certain device. See the section below named
0749 "GPIO mode pitfalls" for more details on this scenario.
0750 
0751 The public pinmux API contains two functions named pinctrl_request_gpio()
0752 and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
0753 gpiolib-based drivers as part of their gpio_request() and
0754 gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
0755 shall only be called from within respective gpio_direction_[input|output]
0756 gpiolib implementation.
0757 
0758 NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
0759 controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
0760 that driver request proper muxing and other control for its pins.
0761 
0762 The function list could become long, especially if you can convert every
0763 individual pin into a GPIO pin independent of any other pins, and then try
0764 the approach to define every pin as a function.
0765 
0766 In this case, the function array would become 64 entries for each GPIO
0767 setting and then the device functions.
0768 
0769 For this reason there are two functions a pin control driver can implement
0770 to enable only GPIO on an individual pin: .gpio_request_enable() and
0771 .gpio_disable_free().
0772 
0773 This function will pass in the affected GPIO range identified by the pin
0774 controller core, so you know which GPIO pins are being affected by the request
0775 operation.
0776 
0777 If your driver needs to have an indication from the framework of whether the
0778 GPIO pin shall be used for input or output you can implement the
0779 .gpio_set_direction() function. As described this shall be called from the
0780 gpiolib driver and the affected GPIO range, pin offset and desired direction
0781 will be passed along to this function.
0782 
0783 Alternatively to using these special functions, it is fully allowed to use
0784 named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
0785 obtain the function "gpioN" where "N" is the global GPIO pin number if no
0786 special GPIO-handler is registered.
0787 
0788 
0789 GPIO mode pitfalls
0790 ==================
0791 
0792 Due to the naming conventions used by hardware engineers, where "GPIO"
0793 is taken to mean different things than what the kernel does, the developer
0794 may be confused by a datasheet talking about a pin being possible to set
0795 into "GPIO mode". It appears that what hardware engineers mean with
0796 "GPIO mode" is not necessarily the use case that is implied in the kernel
0797 interface <linux/gpio.h>: a pin that you grab from kernel code and then
0798 either listen for input or drive high/low to assert/deassert some
0799 external line.
0800 
0801 Rather hardware engineers think that "GPIO mode" means that you can
0802 software-control a few electrical properties of the pin that you would
0803 not be able to control if the pin was in some other mode, such as muxed in
0804 for a device.
0805 
0806 The GPIO portions of a pin and its relation to a certain pin controller
0807 configuration and muxing logic can be constructed in several ways. Here
0808 are two examples:
0809 
0810 (A)
0811                        pin config
0812                        logic regs
0813                        |               +- SPI
0814      Physical pins --- pad --- pinmux -+- I2C
0815                                |       +- mmc
0816                                |       +- GPIO
0817                                pin
0818                                multiplex
0819                                logic regs
0820 
0821 Here some electrical properties of the pin can be configured no matter
0822 whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
0823 pin, you can also drive it high/low from "GPIO" registers.
0824 Alternatively, the pin can be controlled by a certain peripheral, while
0825 still applying desired pin config properties. GPIO functionality is thus
0826 orthogonal to any other device using the pin.
0827 
0828 In this arrangement the registers for the GPIO portions of the pin controller,
0829 or the registers for the GPIO hardware module are likely to reside in a
0830 separate memory range only intended for GPIO driving, and the register
0831 range dealing with pin config and pin multiplexing get placed into a
0832 different memory range and a separate section of the data sheet.
0833 
0834 A flag "strict" in struct pinmux_ops is available to check and deny
0835 simultaneous access to the same pin from GPIO and pin multiplexing
0836 consumers on hardware of this type. The pinctrl driver should set this flag
0837 accordingly.
0838 
0839 (B)
0840 
0841                        pin config
0842                        logic regs
0843                        |               +- SPI
0844      Physical pins --- pad --- pinmux -+- I2C
0845                        |       |       +- mmc
0846                        |       |
0847                        GPIO    pin
0848                                multiplex
0849                                logic regs
0850 
0851 In this arrangement, the GPIO functionality can always be enabled, such that
0852 e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
0853 pulsed out. It is likely possible to disrupt the traffic on the pin by doing
0854 wrong things on the GPIO block, as it is never really disconnected. It is
0855 possible that the GPIO, pin config and pin multiplex registers are placed into
0856 the same memory range and the same section of the data sheet, although that
0857 need not be the case.
0858 
0859 In some pin controllers, although the physical pins are designed in the same
0860 way as (B), the GPIO function still can't be enabled at the same time as the
0861 peripheral functions. So again the "strict" flag should be set, denying
0862 simultaneous activation by GPIO and other muxed in devices.
0863 
0864 From a kernel point of view, however, these are different aspects of the
0865 hardware and shall be put into different subsystems:
0866 
0867 - Registers (or fields within registers) that control electrical
0868   properties of the pin such as biasing and drive strength should be
0869   exposed through the pinctrl subsystem, as "pin configuration" settings.
0870 
0871 - Registers (or fields within registers) that control muxing of signals
0872   from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
0873   be exposed through the pinctrl subsystem, as mux functions.
0874 
0875 - Registers (or fields within registers) that control GPIO functionality
0876   such as setting a GPIO's output value, reading a GPIO's input value, or
0877   setting GPIO pin direction should be exposed through the GPIO subsystem,
0878   and if they also support interrupt capabilities, through the irqchip
0879   abstraction.
0880 
0881 Depending on the exact HW register design, some functions exposed by the
0882 GPIO subsystem may call into the pinctrl subsystem in order to
0883 co-ordinate register settings across HW modules. In particular, this may
0884 be needed for HW with separate GPIO and pin controller HW modules, where
0885 e.g. GPIO direction is determined by a register in the pin controller HW
0886 module rather than the GPIO HW module.
0887 
0888 Electrical properties of the pin such as biasing and drive strength
0889 may be placed at some pin-specific register in all cases or as part
0890 of the GPIO register in case (B) especially. This doesn't mean that such
0891 properties necessarily pertain to what the Linux kernel calls "GPIO".
0892 
0893 Example: a pin is usually muxed in to be used as a UART TX line. But during
0894 system sleep, we need to put this pin into "GPIO mode" and ground it.
0895 
0896 If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
0897 to think that you need to come up with something really complex, that the
0898 pin shall be used for UART TX and GPIO at the same time, that you will grab
0899 a pin control handle and set it to a certain state to enable UART TX to be
0900 muxed in, then twist it over to GPIO mode and use gpio_direction_output()
0901 to drive it low during sleep, then mux it over to UART TX again when you
0902 wake up and maybe even gpio_request/gpio_free as part of this cycle. This
0903 all gets very complicated.
0904 
0905 The solution is to not think that what the datasheet calls "GPIO mode"
0906 has to be handled by the <linux/gpio.h> interface. Instead view this as
0907 a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
0908 and you find this in the documentation:
0909 
0910   PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
0911      1 to indicate high level, argument 0 to indicate low level.
0912 
0913 So it is perfectly possible to push a pin into "GPIO mode" and drive the
0914 line low as part of the usual pin control map. So for example your UART
0915 driver may look like this:
0916 
0917 #include <linux/pinctrl/consumer.h>
0918 
0919 struct pinctrl          *pinctrl;
0920 struct pinctrl_state    *pins_default;
0921 struct pinctrl_state    *pins_sleep;
0922 
0923 pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
0924 pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
0925 
0926 /* Normal mode */
0927 retval = pinctrl_select_state(pinctrl, pins_default);
0928 /* Sleep mode */
0929 retval = pinctrl_select_state(pinctrl, pins_sleep);
0930 
0931 And your machine configuration may look like this:
0932 --------------------------------------------------
0933 
0934 static unsigned long uart_default_mode[] = {
0935     PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
0936 };
0937 
0938 static unsigned long uart_sleep_mode[] = {
0939     PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
0940 };
0941 
0942 static struct pinctrl_map pinmap[] __initdata = {
0943     PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
0944                       "u0_group", "u0"),
0945     PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
0946                         "UART_TX_PIN", uart_default_mode),
0947     PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
0948                       "u0_group", "gpio-mode"),
0949     PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
0950                         "UART_TX_PIN", uart_sleep_mode),
0951 };
0952 
0953 foo_init(void) {
0954     pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
0955 }
0956 
0957 Here the pins we want to control are in the "u0_group" and there is some
0958 function called "u0" that can be enabled on this group of pins, and then
0959 everything is UART business as usual. But there is also some function
0960 named "gpio-mode" that can be mapped onto the same pins to move them into
0961 GPIO mode.
0962 
0963 This will give the desired effect without any bogus interaction with the
0964 GPIO subsystem. It is just an electrical configuration used by that device
0965 when going to sleep, it might imply that the pin is set into something the
0966 datasheet calls "GPIO mode", but that is not the point: it is still used
0967 by that UART device to control the pins that pertain to that very UART
0968 driver, putting them into modes needed by the UART. GPIO in the Linux
0969 kernel sense are just some 1-bit line, and is a different use case.
0970 
0971 How the registers are poked to attain the push or pull, and output low
0972 configuration and the muxing of the "u0" or "gpio-mode" group onto these
0973 pins is a question for the driver.
0974 
0975 Some datasheets will be more helpful and refer to the "GPIO mode" as
0976 "low power mode" rather than anything to do with GPIO. This often means
0977 the same thing electrically speaking, but in this latter case the
0978 software engineers will usually quickly identify that this is some
0979 specific muxing or configuration rather than anything related to the GPIO
0980 API.
0981 
0982 
0983 Board/machine configuration
0984 ==================================
0985 
0986 Boards and machines define how a certain complete running system is put
0987 together, including how GPIOs and devices are muxed, how regulators are
0988 constrained and how the clock tree looks. Of course pinmux settings are also
0989 part of this.
0990 
0991 A pin controller configuration for a machine looks pretty much like a simple
0992 regulator configuration, so for the example array above we want to enable i2c
0993 and spi on the second function mapping:
0994 
0995 #include <linux/pinctrl/machine.h>
0996 
0997 static const struct pinctrl_map mapping[] __initconst = {
0998         {
0999                 .dev_name = "foo-spi.0",
1000                 .name = PINCTRL_STATE_DEFAULT,
1001                 .type = PIN_MAP_TYPE_MUX_GROUP,
1002                 .ctrl_dev_name = "pinctrl-foo",
1003                 .data.mux.function = "spi0",
1004         },
1005         {
1006                 .dev_name = "foo-i2c.0",
1007                 .name = PINCTRL_STATE_DEFAULT,
1008                 .type = PIN_MAP_TYPE_MUX_GROUP,
1009                 .ctrl_dev_name = "pinctrl-foo",
1010                 .data.mux.function = "i2c0",
1011         },
1012         {
1013                 .dev_name = "foo-mmc.0",
1014                 .name = PINCTRL_STATE_DEFAULT,
1015                 .type = PIN_MAP_TYPE_MUX_GROUP,
1016                 .ctrl_dev_name = "pinctrl-foo",
1017                 .data.mux.function = "mmc0",
1018         },
1019 };
1020 
1021 The dev_name here matches to the unique device name that can be used to look
1022 up the device struct (just like with clockdev or regulators). The function name
1023 must match a function provided by the pinmux driver handling this pin range.
1024 
1025 As you can see we may have several pin controllers on the system and thus
1026 we need to specify which one of them contains the functions we wish to map.
1027 
1028 You register this pinmux mapping to the pinmux subsystem by simply:
1029 
1030        ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1031 
1032 Since the above construct is pretty common there is a helper macro to make
1033 it even more compact which assumes you want to use pinctrl-foo and position
1034 0 for mapping, for example:
1035 
1036 static struct pinctrl_map mapping[] __initdata = {
1037         PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1038 };
1039 
1040 The mapping table may also contain pin configuration entries. It's common for
1041 each pin/group to have a number of configuration entries that affect it, so
1042 the table entries for configuration reference an array of config parameters
1043 and values. An example using the convenience macros is shown below:
1044 
1045 static unsigned long i2c_grp_configs[] = {
1046         FOO_PIN_DRIVEN,
1047         FOO_PIN_PULLUP,
1048 };
1049 
1050 static unsigned long i2c_pin_configs[] = {
1051         FOO_OPEN_COLLECTOR,
1052         FOO_SLEW_RATE_SLOW,
1053 };
1054 
1055 static struct pinctrl_map mapping[] __initdata = {
1056         PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
1057         PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1058         PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1059         PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1060 };
1061 
1062 Finally, some devices expect the mapping table to contain certain specific
1063 named states. When running on hardware that doesn't need any pin controller
1064 configuration, the mapping table must still contain those named states, in
1065 order to explicitly indicate that the states were provided and intended to
1066 be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1067 a named state without causing any pin controller to be programmed:
1068 
1069 static struct pinctrl_map mapping[] __initdata = {
1070         PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1071 };
1072 
1073 
1074 Complex mappings
1075 ================
1076 
1077 As it is possible to map a function to different groups of pins an optional
1078 .group can be specified like this:
1079 
1080 ...
1081 {
1082         .dev_name = "foo-spi.0",
1083         .name = "spi0-pos-A",
1084         .type = PIN_MAP_TYPE_MUX_GROUP,
1085         .ctrl_dev_name = "pinctrl-foo",
1086         .function = "spi0",
1087         .group = "spi0_0_grp",
1088 },
1089 {
1090         .dev_name = "foo-spi.0",
1091         .name = "spi0-pos-B",
1092         .type = PIN_MAP_TYPE_MUX_GROUP,
1093         .ctrl_dev_name = "pinctrl-foo",
1094         .function = "spi0",
1095         .group = "spi0_1_grp",
1096 },
1097 ...
1098 
1099 This example mapping is used to switch between two positions for spi0 at
1100 runtime, as described further below under the heading "Runtime pinmuxing".
1101 
1102 Further it is possible for one named state to affect the muxing of several
1103 groups of pins, say for example in the mmc0 example above, where you can
1104 additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1105 three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1106 case), we define a mapping like this:
1107 
1108 ...
1109 {
1110         .dev_name = "foo-mmc.0",
1111         .name = "2bit"
1112         .type = PIN_MAP_TYPE_MUX_GROUP,
1113         .ctrl_dev_name = "pinctrl-foo",
1114         .function = "mmc0",
1115         .group = "mmc0_1_grp",
1116 },
1117 {
1118         .dev_name = "foo-mmc.0",
1119         .name = "4bit"
1120         .type = PIN_MAP_TYPE_MUX_GROUP,
1121         .ctrl_dev_name = "pinctrl-foo",
1122         .function = "mmc0",
1123         .group = "mmc0_1_grp",
1124 },
1125 {
1126         .dev_name = "foo-mmc.0",
1127         .name = "4bit"
1128         .type = PIN_MAP_TYPE_MUX_GROUP,
1129         .ctrl_dev_name = "pinctrl-foo",
1130         .function = "mmc0",
1131         .group = "mmc0_2_grp",
1132 },
1133 {
1134         .dev_name = "foo-mmc.0",
1135         .name = "8bit"
1136         .type = PIN_MAP_TYPE_MUX_GROUP,
1137         .ctrl_dev_name = "pinctrl-foo",
1138         .function = "mmc0",
1139         .group = "mmc0_1_grp",
1140 },
1141 {
1142         .dev_name = "foo-mmc.0",
1143         .name = "8bit"
1144         .type = PIN_MAP_TYPE_MUX_GROUP,
1145         .ctrl_dev_name = "pinctrl-foo",
1146         .function = "mmc0",
1147         .group = "mmc0_2_grp",
1148 },
1149 {
1150         .dev_name = "foo-mmc.0",
1151         .name = "8bit"
1152         .type = PIN_MAP_TYPE_MUX_GROUP,
1153         .ctrl_dev_name = "pinctrl-foo",
1154         .function = "mmc0",
1155         .group = "mmc0_3_grp",
1156 },
1157 ...
1158 
1159 The result of grabbing this mapping from the device with something like
1160 this (see next paragraph):
1161 
1162         p = devm_pinctrl_get(dev);
1163         s = pinctrl_lookup_state(p, "8bit");
1164         ret = pinctrl_select_state(p, s);
1165 
1166 or more simply:
1167 
1168         p = devm_pinctrl_get_select(dev, "8bit");
1169 
1170 Will be that you activate all the three bottom records in the mapping at
1171 once. Since they share the same name, pin controller device, function and
1172 device, and since we allow multiple groups to match to a single device, they
1173 all get selected, and they all get enabled and disable simultaneously by the
1174 pinmux core.
1175 
1176 
1177 Pin control requests from drivers
1178 =================================
1179 
1180 When a device driver is about to probe the device core will automatically
1181 attempt to issue pinctrl_get_select_default() on these devices.
1182 This way driver writers do not need to add any of the boilerplate code
1183 of the type found below. However when doing fine-grained state selection
1184 and not using the "default" state, you may have to do some device driver
1185 handling of the pinctrl handles and states.
1186 
1187 So if you just want to put the pins for a certain device into the default
1188 state and be done with it, there is nothing you need to do besides
1189 providing the proper mapping table. The device core will take care of
1190 the rest.
1191 
1192 Generally it is discouraged to let individual drivers get and enable pin
1193 control. So if possible, handle the pin control in platform code or some other
1194 place where you have access to all the affected struct device * pointers. In
1195 some cases where a driver needs to e.g. switch between different mux mappings
1196 at runtime this is not possible.
1197 
1198 A typical case is if a driver needs to switch bias of pins from normal
1199 operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1200 PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1201 current in sleep mode.
1202 
1203 A driver may request a certain control state to be activated, usually just the
1204 default state like this:
1205 
1206 #include <linux/pinctrl/consumer.h>
1207 
1208 struct foo_state {
1209        struct pinctrl *p;
1210        struct pinctrl_state *s;
1211        ...
1212 };
1213 
1214 foo_probe()
1215 {
1216         /* Allocate a state holder named "foo" etc */
1217         struct foo_state *foo = ...;
1218 
1219         foo->p = devm_pinctrl_get(&device);
1220         if (IS_ERR(foo->p)) {
1221                 /* FIXME: clean up "foo" here */
1222                 return PTR_ERR(foo->p);
1223         }
1224 
1225         foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1226         if (IS_ERR(foo->s)) {
1227                 /* FIXME: clean up "foo" here */
1228                 return PTR_ERR(s);
1229         }
1230 
1231         ret = pinctrl_select_state(foo->s);
1232         if (ret < 0) {
1233                 /* FIXME: clean up "foo" here */
1234                 return ret;
1235         }
1236 }
1237 
1238 This get/lookup/select/put sequence can just as well be handled by bus drivers
1239 if you don't want each and every driver to handle it and you know the
1240 arrangement on your bus.
1241 
1242 The semantics of the pinctrl APIs are:
1243 
1244 - pinctrl_get() is called in process context to obtain a handle to all pinctrl
1245   information for a given client device. It will allocate a struct from the
1246   kernel memory to hold the pinmux state. All mapping table parsing or similar
1247   slow operations take place within this API.
1248 
1249 - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1250   to be called automatically on the retrieved pointer when the associated
1251   device is removed. It is recommended to use this function over plain
1252   pinctrl_get().
1253 
1254 - pinctrl_lookup_state() is called in process context to obtain a handle to a
1255   specific state for a client device. This operation may be slow, too.
1256 
1257 - pinctrl_select_state() programs pin controller hardware according to the
1258   definition of the state as given by the mapping table. In theory, this is a
1259   fast-path operation, since it only involved blasting some register settings
1260   into hardware. However, note that some pin controllers may have their
1261   registers on a slow/IRQ-based bus, so client devices should not assume they
1262   can call pinctrl_select_state() from non-blocking contexts.
1263 
1264 - pinctrl_put() frees all information associated with a pinctrl handle.
1265 
1266 - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1267   explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1268   However, use of this function will be rare, due to the automatic cleanup
1269   that will occur even without calling it.
1270 
1271   pinctrl_get() must be paired with a plain pinctrl_put().
1272   pinctrl_get() may not be paired with devm_pinctrl_put().
1273   devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1274   devm_pinctrl_get() may not be paired with plain pinctrl_put().
1275 
1276 Usually the pin control core handled the get/put pair and call out to the
1277 device drivers bookkeeping operations, like checking available functions and
1278 the associated pins, whereas select_state pass on to the pin controller
1279 driver which takes care of activating and/or deactivating the mux setting by
1280 quickly poking some registers.
1281 
1282 The pins are allocated for your device when you issue the devm_pinctrl_get()
1283 call, after this you should be able to see this in the debugfs listing of all
1284 pins.
1285 
1286 NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1287 requested pinctrl handles, for example if the pinctrl driver has not yet
1288 registered. Thus make sure that the error path in your driver gracefully
1289 cleans up and is ready to retry the probing later in the startup process.
1290 
1291 
1292 Drivers needing both pin control and GPIOs
1293 ==========================================
1294 
1295 Again, it is discouraged to let drivers lookup and select pin control states
1296 themselves, but again sometimes this is unavoidable.
1297 
1298 So say that your driver is fetching its resources like this:
1299 
1300 #include <linux/pinctrl/consumer.h>
1301 #include <linux/gpio.h>
1302 
1303 struct pinctrl *pinctrl;
1304 int gpio;
1305 
1306 pinctrl = devm_pinctrl_get_select_default(&dev);
1307 gpio = devm_gpio_request(&dev, 14, "foo");
1308 
1309 Here we first request a certain pin state and then request GPIO 14 to be
1310 used. If you're using the subsystems orthogonally like this, you should
1311 nominally always get your pinctrl handle and select the desired pinctrl
1312 state BEFORE requesting the GPIO. This is a semantic convention to avoid
1313 situations that can be electrically unpleasant, you will certainly want to
1314 mux in and bias pins in a certain way before the GPIO subsystems starts to
1315 deal with them.
1316 
1317 The above can be hidden: using the device core, the pinctrl core may be
1318 setting up the config and muxing for the pins right before the device is
1319 probing, nevertheless orthogonal to the GPIO subsystem.
1320 
1321 But there are also situations where it makes sense for the GPIO subsystem
1322 to communicate directly with the pinctrl subsystem, using the latter as a
1323 back-end. This is when the GPIO driver may call out to the functions
1324 described in the section "Pin control interaction with the GPIO subsystem"
1325 above. This only involves per-pin multiplexing, and will be completely
1326 hidden behind the gpio_*() function namespace. In this case, the driver
1327 need not interact with the pin control subsystem at all.
1328 
1329 If a pin control driver and a GPIO driver is dealing with the same pins
1330 and the use cases involve multiplexing, you MUST implement the pin controller
1331 as a back-end for the GPIO driver like this, unless your hardware design
1332 is such that the GPIO controller can override the pin controller's
1333 multiplexing state through hardware without the need to interact with the
1334 pin control system.
1335 
1336 
1337 System pin control hogging
1338 ==========================
1339 
1340 Pin control map entries can be hogged by the core when the pin controller
1341 is registered. This means that the core will attempt to call pinctrl_get(),
1342 lookup_state() and select_state() on it immediately after the pin control
1343 device has been registered.
1344 
1345 This occurs for mapping table entries where the client device name is equal
1346 to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1347 
1348 {
1349         .dev_name = "pinctrl-foo",
1350         .name = PINCTRL_STATE_DEFAULT,
1351         .type = PIN_MAP_TYPE_MUX_GROUP,
1352         .ctrl_dev_name = "pinctrl-foo",
1353         .function = "power_func",
1354 },
1355 
1356 Since it may be common to request the core to hog a few always-applicable
1357 mux settings on the primary pin controller, there is a convenience macro for
1358 this:
1359 
1360 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1361 
1362 This gives the exact same result as the above construction.
1363 
1364 
1365 Runtime pinmuxing
1366 =================
1367 
1368 It is possible to mux a certain function in and out at runtime, say to move
1369 an SPI port from one set of pins to another set of pins. Say for example for
1370 spi0 in the example above, we expose two different groups of pins for the same
1371 function, but with different named in the mapping as described under
1372 "Advanced mapping" above. So that for an SPI device, we have two states named
1373 "pos-A" and "pos-B".
1374 
1375 This snippet first initializes a state object for both groups (in foo_probe()),
1376 then muxes the function in the pins defined by group A, and finally muxes it in
1377 on the pins defined by group B:
1378 
1379 #include <linux/pinctrl/consumer.h>
1380 
1381 struct pinctrl *p;
1382 struct pinctrl_state *s1, *s2;
1383 
1384 foo_probe()
1385 {
1386         /* Setup */
1387         p = devm_pinctrl_get(&device);
1388         if (IS_ERR(p))
1389                 ...
1390 
1391         s1 = pinctrl_lookup_state(foo->p, "pos-A");
1392         if (IS_ERR(s1))
1393                 ...
1394 
1395         s2 = pinctrl_lookup_state(foo->p, "pos-B");
1396         if (IS_ERR(s2))
1397                 ...
1398 }
1399 
1400 foo_switch()
1401 {
1402         /* Enable on position A */
1403         ret = pinctrl_select_state(s1);
1404         if (ret < 0)
1405             ...
1406 
1407         ...
1408 
1409         /* Enable on position B */
1410         ret = pinctrl_select_state(s2);
1411         if (ret < 0)
1412             ...
1413 
1414         ...
1415 }
1416 
1417 The above has to be done from process context. The reservation of the pins
1418 will be done when the state is activated, so in effect one specific pin
1419 can be used by different functions at different times on a running system.