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0001 On some platforms, so-called memory-mapped I/O is weakly ordered.  On such
0002 platforms, driver writers are responsible for ensuring that I/O writes to
0003 memory-mapped addresses on their device arrive in the order intended.  This is
0004 typically done by reading a 'safe' device or bridge register, causing the I/O
0005 chipset to flush pending writes to the device before any reads are posted.  A
0006 driver would usually use this technique immediately prior to the exit of a
0007 critical section of code protected by spinlocks.  This would ensure that
0008 subsequent writes to I/O space arrived only after all prior writes (much like a
0009 memory barrier op, mb(), only with respect to I/O).
0010 
0011 A more concrete example from a hypothetical device driver:
0012 
0013         ...
0014 CPU A:  spin_lock_irqsave(&dev_lock, flags)
0015 CPU A:  val = readl(my_status);
0016 CPU A:  ...
0017 CPU A:  writel(newval, ring_ptr);
0018 CPU A:  spin_unlock_irqrestore(&dev_lock, flags)
0019         ...
0020 CPU B:  spin_lock_irqsave(&dev_lock, flags)
0021 CPU B:  val = readl(my_status);
0022 CPU B:  ...
0023 CPU B:  writel(newval2, ring_ptr);
0024 CPU B:  spin_unlock_irqrestore(&dev_lock, flags)
0025         ...
0026 
0027 In the case above, the device may receive newval2 before it receives newval,
0028 which could cause problems.  Fixing it is easy enough though:
0029 
0030         ...
0031 CPU A:  spin_lock_irqsave(&dev_lock, flags)
0032 CPU A:  val = readl(my_status);
0033 CPU A:  ...
0034 CPU A:  writel(newval, ring_ptr);
0035 CPU A:  (void)readl(safe_register); /* maybe a config register? */
0036 CPU A:  spin_unlock_irqrestore(&dev_lock, flags)
0037         ...
0038 CPU B:  spin_lock_irqsave(&dev_lock, flags)
0039 CPU B:  val = readl(my_status);
0040 CPU B:  ...
0041 CPU B:  writel(newval2, ring_ptr);
0042 CPU B:  (void)readl(safe_register); /* maybe a config register? */
0043 CPU B:  spin_unlock_irqrestore(&dev_lock, flags)
0044 
0045 Here, the reads from safe_register will cause the I/O chipset to flush any
0046 pending writes before actually posting the read to the chipset, preventing
0047 possible data corruption.