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0001 Linux IOMMU Support
0002 ===================
0003 
0004 The architecture spec can be obtained from the below location.
0005 
0006 http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
0007 
0008 This guide gives a quick cheat sheet for some basic understanding.
0009 
0010 Some Keywords
0011 
0012 DMAR - DMA remapping
0013 DRHD - DMA Remapping Hardware Unit Definition
0014 RMRR - Reserved memory Region Reporting Structure
0015 ZLR  - Zero length reads from PCI devices
0016 IOVA - IO Virtual address.
0017 
0018 Basic stuff
0019 -----------
0020 
0021 ACPI enumerates and lists the different DMA engines in the platform, and
0022 device scope relationships between PCI devices and which DMA engine  controls
0023 them.
0024 
0025 What is RMRR?
0026 -------------
0027 
0028 There are some devices the BIOS controls, for e.g USB devices to perform
0029 PS2 emulation. The regions of memory used for these devices are marked
0030 reserved in the e820 map. When we turn on DMA translation, DMA to those
0031 regions will fail. Hence BIOS uses RMRR to specify these regions along with
0032 devices that need to access these regions. OS is expected to setup
0033 unity mappings for these regions for these devices to access these regions.
0034 
0035 How is IOVA generated?
0036 ---------------------
0037 
0038 Well behaved drivers call pci_map_*() calls before sending command to device
0039 that needs to perform DMA. Once DMA is completed and mapping is no longer
0040 required, device performs a pci_unmap_*() calls to unmap the region.
0041 
0042 The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
0043 device has its own domain (hence protection). Devices under p2p bridges
0044 share the virtual address with all devices under the p2p bridge due to
0045 transaction id aliasing for p2p bridges.
0046 
0047 IOVA generation is pretty generic. We used the same technique as vmalloc()
0048 but these are not global address spaces, but separate for each domain.
0049 Different DMA engines may support different number of domains.
0050 
0051 We also allocate guard pages with each mapping, so we can attempt to catch
0052 any overflow that might happen.
0053 
0054 
0055 Graphics Problems?
0056 ------------------
0057 If you encounter issues with graphics devices, you can try adding
0058 option intel_iommu=igfx_off to turn off the integrated graphics engine.
0059 If this fixes anything, please ensure you file a bug reporting the problem.
0060 
0061 Some exceptions to IOVA
0062 -----------------------
0063 Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
0064 The same is true for peer to peer transactions. Hence we reserve the
0065 address from PCI MMIO ranges so they are not allocated for IOVA addresses.
0066 
0067 
0068 Fault reporting
0069 ---------------
0070 When errors are reported, the DMA engine signals via an interrupt. The fault
0071 reason and device that caused it with fault reason is printed on console.
0072 
0073 See below for sample.
0074 
0075 
0076 Boot Message Sample
0077 -------------------
0078 
0079 Something like this gets printed indicating presence of DMAR tables
0080 in ACPI.
0081 
0082 ACPI: DMAR (v001 A M I  OEMDMAR  0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
0083 
0084 When DMAR is being processed and initialized by ACPI, prints DMAR locations
0085 and any RMRR's processed.
0086 
0087 ACPI DMAR:Host address width 36
0088 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
0089 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
0090 ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
0091 ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
0092 ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
0093 
0094 When DMAR is enabled for use, you will notice..
0095 
0096 PCI-DMA: Using DMAR IOMMU
0097 
0098 Fault reporting
0099 ---------------
0100 
0101 DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
0102 DMAR:[fault reason 05] PTE Write access is not set
0103 DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
0104 DMAR:[fault reason 05] PTE Write access is not set
0105 
0106 TBD
0107 ----
0108 
0109 - For compatibility testing, could use unity map domain for all devices, just
0110   provide a 1-1 for all useful memory under a single domain for all devices.
0111 - API for paravirt ops for abstracting functionality for VMM folks.