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0001                         DMA attributes
0002                         ==============
0003 
0004 This document describes the semantics of the DMA attributes that are
0005 defined in linux/dma-mapping.h.
0006 
0007 DMA_ATTR_WRITE_BARRIER
0008 ----------------------
0009 
0010 DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA
0011 to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
0012 all pending DMA writes to complete, and thus provides a mechanism to
0013 strictly order DMA from a device across all intervening busses and
0014 bridges.  This barrier is not specific to a particular type of
0015 interconnect, it applies to the system as a whole, and so its
0016 implementation must account for the idiosyncrasies of the system all
0017 the way from the DMA device to memory.
0018 
0019 As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
0020 useful, suppose that a device does a DMA write to indicate that data is
0021 ready and available in memory.  The DMA of the "completion indication"
0022 could race with data DMA.  Mapping the memory used for completion
0023 indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
0024 
0025 DMA_ATTR_WEAK_ORDERING
0026 ----------------------
0027 
0028 DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
0029 may be weakly ordered, that is that reads and writes may pass each other.
0030 
0031 Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
0032 those that do not will simply ignore the attribute and exhibit default
0033 behavior.
0034 
0035 DMA_ATTR_WRITE_COMBINE
0036 ----------------------
0037 
0038 DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
0039 buffered to improve performance.
0040 
0041 Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
0042 those that do not will simply ignore the attribute and exhibit default
0043 behavior.
0044 
0045 DMA_ATTR_NON_CONSISTENT
0046 -----------------------
0047 
0048 DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
0049 consistent or non-consistent memory as it sees fit.  By using this API,
0050 you are guaranteeing to the platform that you have all the correct and
0051 necessary sync points for this memory in the driver.
0052 
0053 DMA_ATTR_NO_KERNEL_MAPPING
0054 --------------------------
0055 
0056 DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
0057 virtual mapping for the allocated buffer. On some architectures creating
0058 such mapping is non-trivial task and consumes very limited resources
0059 (like kernel virtual address space or dma consistent address space).
0060 Buffers allocated with this attribute can be only passed to user space
0061 by calling dma_mmap_attrs(). By using this API, you are guaranteeing
0062 that you won't dereference the pointer returned by dma_alloc_attr(). You
0063 can treat it as a cookie that must be passed to dma_mmap_attrs() and
0064 dma_free_attrs(). Make sure that both of these also get this attribute
0065 set on each call.
0066 
0067 Since it is optional for platforms to implement
0068 DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
0069 attribute and exhibit default behavior.
0070 
0071 DMA_ATTR_SKIP_CPU_SYNC
0072 ----------------------
0073 
0074 By default dma_map_{single,page,sg} functions family transfer a given
0075 buffer from CPU domain to device domain. Some advanced use cases might
0076 require sharing a buffer between more than one device. This requires
0077 having a mapping created separately for each device and is usually
0078 performed by calling dma_map_{single,page,sg} function more than once
0079 for the given buffer with device pointer to each device taking part in
0080 the buffer sharing. The first call transfers a buffer from 'CPU' domain
0081 to 'device' domain, what synchronizes CPU caches for the given region
0082 (usually it means that the cache has been flushed or invalidated
0083 depending on the dma direction). However, next calls to
0084 dma_map_{single,page,sg}() for other devices will perform exactly the
0085 same synchronization operation on the CPU cache. CPU cache synchronization
0086 might be a time consuming operation, especially if the buffers are
0087 large, so it is highly recommended to avoid it if possible.
0088 DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
0089 the CPU cache for the given buffer assuming that it has been already
0090 transferred to 'device' domain. This attribute can be also used for
0091 dma_unmap_{single,page,sg} functions family to force buffer to stay in
0092 device domain after releasing a mapping for it. Use this attribute with
0093 care!
0094 
0095 DMA_ATTR_FORCE_CONTIGUOUS
0096 -------------------------
0097 
0098 By default DMA-mapping subsystem is allowed to assemble the buffer
0099 allocated by dma_alloc_attrs() function from individual pages if it can
0100 be mapped as contiguous chunk into device dma address space. By
0101 specifying this attribute the allocated buffer is forced to be contiguous
0102 also in physical memory.
0103 
0104 DMA_ATTR_ALLOC_SINGLE_PAGES
0105 ---------------------------
0106 
0107 This is a hint to the DMA-mapping subsystem that it's probably not worth
0108 the time to try to allocate memory to in a way that gives better TLB
0109 efficiency (AKA it's not worth trying to build the mapping out of larger
0110 pages).  You might want to specify this if:
0111 - You know that the accesses to this memory won't thrash the TLB.
0112   You might know that the accesses are likely to be sequential or
0113   that they aren't sequential but it's unlikely you'll ping-pong
0114   between many addresses that are likely to be in different physical
0115   pages.
0116 - You know that the penalty of TLB misses while accessing the
0117   memory will be small enough to be inconsequential.  If you are
0118   doing a heavy operation like decryption or decompression this
0119   might be the case.
0120 - You know that the DMA mapping is fairly transitory.  If you expect
0121   the mapping to have a short lifetime then it may be worth it to
0122   optimize allocation (avoid coming up with large pages) instead of
0123   getting the slight performance win of larger pages.
0124 Setting this hint doesn't guarantee that you won't get huge pages, but it
0125 means that we won't try quite as hard to get them.
0126 
0127 NOTE: At the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM,
0128 though ARM64 patches will likely be posted soon.
0129 
0130 DMA_ATTR_NO_WARN
0131 ----------------
0132 
0133 This tells the DMA-mapping subsystem to suppress allocation failure reports
0134 (similarly to __GFP_NOWARN).
0135 
0136 On some architectures allocation failures are reported with error messages
0137 to the system logs.  Although this can help to identify and debug problems,
0138 drivers which handle failures (eg, retry later) have no problems with them,
0139 and can actually flood the system logs with error messages that aren't any
0140 problem at all, depending on the implementation of the retry mechanism.
0141 
0142 So, this provides a way for drivers to avoid those error messages on calls
0143 where allocation failures are not a problem, and shouldn't bother the logs.
0144 
0145 NOTE: At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.